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PDF ( 数据手册 , 数据表 ) WD90C00

零件编号 WD90C00
描述 VGA Controller
制造商 Western Digital
LOGO Western Digital LOGO 


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WD90C00 数据手册, 描述, 功能







WD90C00 pdf, 数据表
WD90COO
ARCHITECTURE
2.0 ARCHITECTURE
The WD90COO is a highly integrated device that
internally contains four major modules. These
are the CRT Controller, the Sequencer, the
Graphics controller and the Attribute Controller.
• CRT Controller
The CRT Controller maintains screen refresh ..
functions for the various display modes defined
by the programming of its registers either by the
BIOS ROM resident firmware or from the applica-
tion program. These screen refresh functions in-
clude display page control, cursor control, sync
generation and resolution.
• Sequencer
The Sequencer functions as a timing generator
for the AT bus or Micro Channel interface, in I/O
or memory cycles. It also provides the character
clock and the dot clock for the CRT, Graphics and
Attribute controllers.
• Graphics Controller
The Graphics Controller manages data flow be-
tween video memory and the Attribute Controller
during active display (non-blanked) periods. It
also controls system microprocessor reads from
and writes to the video memory, using the time
slots defined by the Sequencer.
• Attribute Controller
The Attribute Controller modifies the CRT display
data stream in graphics and character modes. It
controls display attributes such as blinking, under-
lining, cursor, pixel panning, reverse video, over-
scan color and background or foreground color.
I AT I UCA
INTERfACE
I
J
I BlOB
ROM
'"1
I EXTlD8C,
L "we
f-
I
WD90COO
I DR••
CONnR
,'',."R1
I' - - -
VIDIO·7)
DATA
'o.,~
CLOCK
comR
11 CRT
CQN1lR
VIDEO
MEMORY
UPT
1 US
ANALOG/DIGITAL
COlORIMONO MONITOR
l FIXED OR
VAAIABLE
SCAN
j
I
12-4
FIGURE 2. SYSTEM BLOCK DIAGRAM
10-25-90







WD90C00 equivalent, schematic
WD90COO
PIN NO.
89
90
91
92
93
94
95
96
97
98
99
2
3
4
5
6
63
65
66
67
68
69
70
71
72
80
83
79
PIN DESCRIPTION
PIN SYMBOL TYPE DESCRIPTION
VIDEO MEMORY DATA
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MOO
1/0 DISPLAY MEMORY DATA MD(15:0): These
lines are the data bus to the video display
DRAMS. Data lines MD(7:0) are pulled up or
down with resistors to provide set up informa-
tion on power-up (reset) as follows:
Power-Up
Register
Me! Fum.liQo
(Bil)
15 EGASW4
PR11 (7)+
14 EGASW3
PR11(6)+
13 EGASW2
PR11 (5)+
12 EGASW1
PR11 (4)+
11 ANALOG/TTL Display CNF(8) *
7 General Purpose
CNF(7) *
6 General Purpose
CNF(6) *
5 General Purpose
CNF(5) *
4 General Purpose
CNF(4) *
3 VCLK1 ,2 InpuVOutput CNF(3) +
2 AT/MicroChannel Mode CNF(2) +
1 BIOS ROM Data Path PR1 (1) *
0 BIOS ROM Mapout
PR1(0) *
NOTE:
"." Pulldown resistor sets these bits to logic 1.
"+" Pullup resistor sets these bits to logic 1.
For more details refer to PR Registers.
VIDEO MEMORY ADDRESS
MA8+
MA7+
MA6+
MA5+
MA4+
MA3+
MA2+
MA1+
MAO+
0 MEMORY ADDRESS MA(8:0): Display
memory DRAM address.
NOTE: "+" For testing purposes, these pins
can be tri-stated by setting PR Register PR4(4)
= 1.
VIDEO MEMORY CONTROL SIGNALS
CAS10+
CAS32+
RAS10+
0 COLUMN ADDRESS STROBE: Active low
Memory Maps 1 & 0 CAS output signal.
0 COLUMN ADDRESS STROBE: Active low
memory maps 3 & 2 CAS output signal.
0 ROW ADDRESS STROBE: Active low
Memory Maps 1 & 0 RAS output siQnal.
12-12
10-25-90










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