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PDF ( 数据手册 , 数据表 ) NB4N121K

零件编号 NB4N121K
描述 3.3V Differential 1:21 Differential Fanout Clock Driver
制造商 ON Semiconductor
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NB4N121K 数据手册, 描述, 功能
NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Singleended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
Additive Phase RMS Jitter: 1 ps Max
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Level (700 mV PeaktoPeak)
PbFree Packages are Available
http://onsemi.com
1 52
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
52
1
NB4N
121K
AWLYYWWG
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
VTCLK
VCC
GND
RREF
Q19
Q20
IREF Q20
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 6
1
Publication Order Number:
NB4N121K/D







NB4N121K pdf, 数据表
VCC
VCC
CML
Driver
Z0 = 50 W
VCC
VTCLK
VTCLK
Z0 = 50 W
NB4N121K
D
50 W*
50 W*
D
GND
VTCLK = VTCLK = VCC
GND
NB4N121K
VCC
VCC
LVCMOS/
LVTTL
Driver
GND
Z0 = 50 W
VTCLK
VTCLK
Vth
NB4N121K
D
50 W*
50 W*
D
VTCLK = OPEN
VTCLK = OPEN
D = Vth
GND
*RTIN, Internal Input Termination Resistor
Figure 12. Standard 50 W Load CML
Interface
VCC
*RTIN, Internal Input Termination Resistor
Figure 13. LVCMOS/LVTTL Interface
VDR
INTQ
INTQb
Q
Qb
Figure 14. HCSL Output Structure
ORDERING INFORMATION
Device
Package
Shipping
NB4N121KMNG
QFN52
(PbFree)
260 Units / Tray
NB4N121KMNR2G
QFN52
(PbFree)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
8














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