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PDF ( 数据手册 , 数据表 ) SH6613D

零件编号 SH6613D
描述 4K 4-Bit Microcontroller
制造商 Sino Wealth
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SH6613D 数据手册, 描述, 功能
SH6613D
4K 4-Bit Microcontroller with LCD Driver
Features
SH6610C-based single-chip 4-bit micro-controller
ROM: 4096×16 bits
RAM: 512×4 bits
Operation voltage: 2.4V – 6.0V
8 CMOS bi-directional I/O pins
4-Level subroutine nesting (include interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power-on reset
Powerful interrupt sources:
- External interrupts ( INT0 ).
- Internal interrupt (Timer0).
- Internal interrupt (Base Timer).
- Port's falling edge interrupt: PORTB ( INT1 )
8-bit Base timer
LCD driver: 136 dots(1/4 duty 1/3 bias)
LCD used as scan output
Built-in dual tone PSG with one noise generator
2 Clock source
OSC: (code option select crystal or RC type)
- Crystal oscillator 32.768K
- RC oscillator: 262K
OSCX: (system register select ceramic or RC type)
- Ceramic oscillator 455K
- RC oscillator 1.8M or 2M
Instruction cycle time:
- 122.07µs for 32.768 kHz crystal
- 15.27µs for 262 kHz RC
- 8.79µs for 455KHz ceramic
- 2.22µs for 1.8 MHz RC
- 2µs for 2.0 MHz RC
Two low power operation mode: HALT and STOP
Low power consumption
General Description
SH6613D is a single chip microcontroller integrated with SRAM, timer and dual-tone PSG, LCD driver and I/O port. This chip
builds in a dual-oscillator to enhance the total chip performance.
Pad Diagram
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SSSSSSSSSSSS
EEEEEEEEEEEE
GGGGGGGGGGGG
112222222222
890123456789
SSS
EEE
GGG
333
012
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
45 28
46 27
47 26
48 25
49 24
50 23
51
SH6613D
22
52 21
53 GND 20
54 19
55 18
56 17
VDD
57 9 16
58 1 2 3 4 5 6 7 8
10 11 12 13 14 15
_
S S S V V V VT RPP P P P P
E E E L 1 2 3 E E C. B. B. B. B. A.
GGGC
321D
S S1 3 21 03
T
E
T
SEG33
SEG34
COM4
COM3
COM2
COM1
OSCI
OSCO
PC.0
OSCXO
OSCXI
PA.0
PA.1
PA.2
1/33 V1.0







SH6613D pdf, 数据表
SH6613D
7.2 Controlling the pull-up MOS
These ports contain pull-up MOS controlled by program. Bit3 of the PMOD register controls On/Off of all pull-up MOS
simultaneously. Pull-up MOS also controlled by the port data registers (PA, PB) of each port also. So the pull-up MOS can be
turned On/Off.
7.3 Port Interrupt
PORTB interrupt (falling edge) is not controlled by Port I/O register. It is means that if a interrupt requestIEx is set to 1 & one
port bit high go lowis been touched and that the condition is the other port bits are high level whenever the port bit is output or
input.
7.4 External INT
PortA.0 is shared by external interrupts (active low).
7.5 Port I/O control register:
Address
$0B
$0C
Bit3
PACR.3
PBCR.3
Bit2
PACR.2
PBCR.2
I/O control register: PACR.X, PBCR.X (X=0,1,2,3)
1: Use as an output buffer.
0: Use as input buffer (Power on initial).
Bit1
PACR.1
PBCR.1
Bit0
PACR.0
PBCR.0
7.6 Port mode register (PMOD)
Bit3
$13 PPULL
Bit2
PAM2
Bit1
PAM1
Bit0
HLM
Function
Bit1,2:Select PA.1,PA.2 as I/O port or PSG output
Bit0:Hevey load mode
Bit3:Port pull-up control
R/W
PAM1, PAM2:
HLM:
PPULL:
Please sees the PSG
Enable heavy load mode 0:Disable
Port pull-up MOS
0:Disable pull-up MOS
1:Enable
1:Enable pull-up MOS
7.7 Heavy load mode (HLM)
The MCU has a heavy load protection circuit for when the battery load becomes heavy. For examples, when an external buzzer
sound or an external speaker is turned on. In this mode, the crystal oscillator circuit has been backup for high gain. When setup
this mode, more power would be provided to oscillator circuit. Unless it is necessary, be careful not to set this mode with
software. Since the mode enter would delay for one instruction. Please activate heavy load driving only after setting HLM at
least one instruction wait cycle through the software. Following shows the programming setting.
HLM: 0=Heavy load protection mode is released
1=Heavy load protection mode is set.
HLM
0
1
HEAVYLOAD
ON
OFF
1 Instruction Cycle Time
8/33 V1.0







SH6613D equivalent, schematic
SH6613D
10. Base Timer
The MCU has a base timer that is shared with the warm-up timer and the clock source is OSC (Low frequency oscillation: X'tal
32.768KHz or RC 262KHz). After MCU is reset, it counts at every clock-input signal. When it counts to $FF, right after next clock
input, counter counts to $00 and generates an overflow This causes the interrupt of base timer interrupt request flag to
1.Therefor, base timer can function as an interval timer periodically, generating overflow output as every 256th clock signal
output.
The timer accepts 4096Hz or 32KHz clock, and base timer generates an accurate timing interrupt. This base time prescaler can
be reset by a program for accurate timing.
This clock-input source is sleeted by BTM register.
Address
$03
Bit3
BTM.3
Bit2
BTM.2
Bit1
BTM.1
Bit0
BTM.0
Function
Base timer mode register
BTM.3=0: Disable the base timer
BTM.2=0: Non reset the base timer
BTM.3=1: Enable the base timer
BTM.2=1: reset the base timer
BTM.1
0
0
1
1
BTM.0
0
1
0
1
Prescaler Ratio
/1
/4
/8
/16
Clock source
4096Hz or 32KHz
4096Hz or 32KHz
4096Hz or 32KHz
4096Hz or 32KHz
MPX
32k
or
262k
/8
/1 /4 /8 /16
4096/32K
4Bit Scaler
8 Bit base timer counter
reset
16/33
V1.0










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