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PDF ( 数据手册 , 数据表 ) PZ5128

零件编号 PZ5128
描述 128 macrocell CPLD
制造商 Philips
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PZ5128 数据手册, 描述, 功能
INTEGRATED CIRCUITS
PZ5128
128 macrocell CPLD
Product specification
Supersedes data of 1997 Apr 28
IC27 Data Handbook
Philips
Semiconductors
1997 Aug 12







PZ5128 pdf, 数据表
Philips Semiconductors
128 macrocell CPLD
Product specification
PZ5128
JTAG Testing Capability
JTAG is the commonly-used acronym for the Boundary Scan Test
(BST) feature defined for integrated circuits by IEEE Standard
1149.1. This standard defines input/output pins, logic control
functions, and commands which facilitate both board and device
level testing without the use of specialized test equipment. BST
provides the ability to test the external connections of a device, test
the internal logic of the device, and capture data from the device
during normal operation. BST provides a number of benefits in each
of the following areas:
Testability
Allows testing of an unlimited number of interconnects on the
printed circuit board
Testability is designed in at the component level
Enables desired signal levels to be set at specific pins (Preload)
Data from pin or core logic signals can be examined during
normal operation
Reliability
Eliminates physical contacts common to existing test fixtures
(e.g., “bed-of-nails”)
Degradation of test equipment is no longer a concern
Facilitates the handling of smaller, surface-mount components
Allows for testing when components exist on both sides of the
printed circuit board
Cost
Reduces/eliminates the need for expensive test equipment
Reduces test preparation time
Reduces spare board inventories
The Philips PZ5128’s JTAG interface includes a TAP Port and a TAP
Controller, both of which are defined by the IEEE 1149.1 JTAG
Specification. As implemented in the Philips PZ5128, the TAP Port
includes four of the five pins (refer to Table 3) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal defined by
the JTAG specification is TRST* (Test Reset). TRST* is considered
an optional signal, since it is not actually required to perform BST or
ISP. The Philips PZ5128 saves an I/O pin for general purpose use
by not implementing the optional TRST* signal in the JTAG
interface. Instead, the Philips PZ5128 supports the test reset
functionality through the use of its power up reset circuit, which is
included in all Philips CPLDs. The pins associated with the power up
reset circuit should connect to an external pull-up resistor to keep
the JTAG signals from floating when they are not being used.
In the Philips PZ5128, the four mandatory JTAG pins each require a
unique, dedicated pin on the device. However, if JTAG and ISP are
not desired in the end-application, these pins may instead be used
as additional general I/O pins. The decision as to whether these pins
are used for JTAG/ISP or as general I/O is made when the JEDEC
file is generated. If the use of JTAG/ISP is selected, the dedicated
pins are not available for general purpose use. However, unlike
competing CPLD’s, the Philips PZ5128 does allow the macrocell
logic associated with these dedicated pins to be used as buried logic
even when JTAG/ISP is selected. Table 4 defines the dedicated pins
used by the four mandatory JTAG signals for each of the PZ5128
package types.
The JTAG specifications defines two sets of commands to support
boundary-scan testing: high-level commands and low-level
commands. High-level commands are executed via board test
software on an a user test station such as automated test
equipment, a PC, or an engineering workstation (EWS). Each
high-level command comprises a sequence of low level commands.
These low-level commands are executed within the component
under test, and therefore must be implemented as part of the TAP
Controller design. The set of low-level boundary-scan commands
implemented in the Philips PZ5128 is defined in Table 5. By
supporting this set of low-level commands, the PZ5128 allows
execution of all high-level boundary-scan commands.
Table 3. JTAG Pin Description
PIN NAME
DESCRIPTION
TCK
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively.
TCK is also used to clock the TAP Controller state machine.
TMS
Test Mode Select
Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode
operation.
TDI Test Data Input
Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK.
TDO
Test Data Output
Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The
signal is tri-stated if data is not being shifted out of the device.
Table 4. PZ5128 JTAG Pinout by Package Type
DEVICE
PZ5128
84-pin PLCC
100-pin PQFP
100-pin TQFP
128-pin LQFP
160-pin PQFP
TCK
62 / 96 (F15)
64 / 96 (F15)
62 / 96 (F15)
82 / 96 (F15)
99 / 96 (F15)
(PIN NUMBER / MACROCELL #)
TMS
TDI
23 / 48 (C15)
17 / 48 (C15)
15 / 48 (C15)
21 / 48 (C15)
22 / 48 (C15)
14 / 32 (B15)
6 / 32 (B15)
4 / 32 (B15)
8 / 32 (B15)
9 / 32 (B15)
TDO
71 / 112 (G15)
75 / 112 (G15)
73 / 112 (G15)
95 / 112 (G15)
112/ 112 (G15)
1997 Aug 12
8







PZ5128 equivalent, schematic
Philips Semiconductors
128 macrocell CPLD
Product specification
PZ5128
160-Pin Plastic Quad Flat Package
160 121
1 120
PQFP
40 81
41 80
Pin Function
1 NC
2 NC
3 NC
4 NC
5 NC
6 NC
7 NC
8 VDD
9 I/O-B15 (TDI)
10 I/O-B13
11 I/O-B12
12 I/O-B11
13 I/O-B10
14 I/O-B8
15 I/O-B7
16 I/O-B5
17 GND
18 I/O-B4
19 I/O-B3
20 I/O-B2
21 I/O-B0
22 I/O-C15 (TMS)
23 I/O-C13
24 I/O-C12
25 I/O-C11
26 VDD
27 I/O-C10
28 I/O-C8
29 I/O-C7
30 I/O-C5
31 I/O-C4
32 I/O-C3
33 I/O-C2
34 NC
35 NC
36 NC
37 NC
38 NC
39 NC
40 NC
41 I/O-C0
42 GND
43 I/O-D15
44 NC
45 NC
46 NC
47 NC
48 I/O-D13
49 I/O-D12
50 I/O-D11
51 I/O-D10
52 I/O-D8
53 I/O-D7
Pin Function
54 I/O-D5
55 VDD
56 I/O-D4
57 I/O-D3
58 I/O-D2
59 I/O-D0/CLK2
60 GND
61 VDD
62 I/O-E0/CLK1
63 I/O-E2
64 I/O-E3
65 I/O-E4
66 GND
67 I/O-E5
68 I/O-E7
69 I/O-E8
70 I/O-E10
71 I/O-E11
72 I/O-E12
73 I/O-E13
74 NC
75 NC
76 NC
77 NC
78 I/O-E15
79 VDD
80 I/O-F0
81 NC
82 NC
83 NC
84 NC
85 NC
86 NC
87 NC
88 I/O-F2
89 I/O-F3
90 I/O-F4
91 I/O-F5
92 I/O-F7
93 I/O-F8
94 I/O-F10
95 GND
96 I/O-F11
97 I/O-F12
98 I/O-F13
99 I/O-F15 (TCK)
100 I/O-G0
101 I/O-G2
102 I/O-G3
103 I/O-G4
104 VDD
105 I/O-G5
106 I/O-G7
* THE TEST MODE SELECT (TMS) FUNCTION IS
INACTIVE ON NON-ISR ARCHITECTURES.
Pin Function
107 I/O-G8
108 I/O-G10
109 I/O-G11
110 I/O-G12
111 I/O-G13
112 I/O-G15 (TDO)
113 GND
114 NC
115 NC
116 NC
117 NC
118 NC
119 NC
120 NC
121 I/O-H0
122 I/O-H2
123 I/O-H3
124 NC
125 NC
126 NC
127 NC
128 I/O-H4
129 I/O-H5
130 I/O-H7
131 I/O-H8
132 I/O-H10
133 VDD
134 I/O-H11
135 I/O-H12
136 I/O-H13
137 I/O-H15
138 GND
139 IN0/CLK0
140 IN2-gtsn
141 IN1
142 IN3
143 VDD
144 I/O-A15/CLK3
145 I/O-A13
146 I/O-A12
147 I/O-A11
148 GND
149 I/O-A10
150 I/O-A8
151 I/O-A7
152 I/O-A5
153 I/O-A4
154 NC
155 NC
156 NC
157 NC
158 I/O-A3
159 I/O-A2
160 I/O-A0
SP00470A
Package Thermal Characteristics
Philips Semiconductors uses the Temperature Sensitive Parameter
(TSP) method to test thermal resistance. This method meets
Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC
Package Databook. Thermal resistance varies slightly as a function
of input power. As input power increases, thermal resistance
changes approximately 5% for a 100% change in power.
Figure 7 is a derating curve for the change in ΘJA with airflow based
on wind tunnel measurements. It should be noted that the wind flow
dynamics are more complex and turbulent in actual applications
than in a wind tunnel. Also, the test boards used in the wind tunnel
contribute significantly to forced convection heat transfer, and may
not be similar to the actual circuit board, especially in size.
Package
84-pin PLCC
100-pin PQFP
100-pin TQFP
128-pin LQFP
160-pin PQFP
ΘJA
32.8 °C/W
41.2 °C/W
47.4 °C/W
45.0 °C/W
31.4 °C/W
PERCENTAGE
REDUCTION IN
ΘJA (%)
0
10
20
30
40
50
0
PLCC/
QFP
1 2 34
AIR FLOW (m/s)
5
SP00419A
Figure 7. Average Effect of Airflow on ΘJA
1997 Aug 12
16










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