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PDF ( 数据手册 , 数据表 ) W83195CG-413

零件编号 W83195CG-413
描述 Clock Generator
制造商 Winbond
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W83195CG-413 数据手册, 描述, 功能
Winbond Clock Generator
W83195WG-413
W83195CG-413
For ATI P4 Chipset
Date: Feb/27/2006 Revision: 0.6







W83195CG-413 pdf, 数据表
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
29 ATIGC0
30 ATIGT0
31 GND
32 VDDATIG
33 SRCC0
34 SRCT0
35 VDDSRC
36 GND
37 IREF
38 GNDA
39 VDDA
40 CPUC2_ITP
41 CPUT2_ITP
42 CPUC1
43 CPUT1
44 GND
45 VDDCPU
46 CPUC0
47 CPUT0
48 *CPU_STOP#
49 GND
50 &CK410#/PCICLK0
51 VDDPCI
52 REF2
53 &FSB/REF1
54 &FSA/REF0
55 GND
56 VDDREF
OUT 0.7V current mode differential clock output for ATIG
OUT 0.7V current mode differential clock output for ATIG
PWR Ground pin
PWR Power supply for ATIG
OUT 0.7V current mode differential clock output for SRC
OUT 0.7V current mode differential clock output for SRC
PWR Power supply for SRC
PWR Ground pin
Deciding the reference current for the differential pairs. The
OUT pin was connected to the precision resistor tied to ground to
decide the appropriate current; 475 ohm is the standard value.
PWR Ground pin for PLL core.
PWR 3.3V power supply for PLL core.
OUT 0.7V current mode differential clock output for CPUC2
OUT 0.7V current mode differential clock output for CPUT2
OUT 0.7V current mode differential clock output for CPUC1
OUT 0.7V current mode differential clock output for CPUT1
PWR Ground pin
PWR Power supply for CPU
OUT 0.7V current mode differential clock output for CPUC0
OUT 0.7V current mode differential clock output for CPUT0
IN Stop selected CPUCLK.
PWR Ground pin
I/O
FS Table select latch input pin / 3.3V PCI clock output.
0 = CK410 FS Table, 1 = CK409 FS Table
PWR Power supply for PCI
OUT   3.3V REF 14.318Mhz clock output.
I/O FSB CPU frequency select/3.3V REF 14.318Mhz clock output.
I/O FSA CPU frequency select/3.3V REF 14.318Mhz clock output.
PWR Ground pin
PWR Power supply for REF
Publication Release Date: Feb 2006
- 4 - Revision 0.6







W83195CG-413 equivalent, schematic
W83195WG-413/W83195CG-413
STEPLESS FOR ATI P4 CLOCK GENERATOR
7.13 Register 12: ( Default : XXh )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
7 Reserved
6 KVAL<9>
5 KVAL<5>
0 Reserved
X Define the PCI divider ratio
Table-2 integrate the all divider configuration
X
4 KVAL<4>
3 KVAL<3>
X Define the SRC divider ratio
Refer to Table-2
X
2 KVAL<2>
1 KVAL<1>
0 KVAL<0>
X
Define the CPU divider ratio
X
Refer to Table-2
X
TYPE
R/W
R/W
R/W
R/W
Table-2 CPU, SRC, PCI divider ratio selection Table
LSB
PCI
SRC
Bit5 Bit3
MSB
0101
Bit2/
Bit4/
Bit9
0 Reserved Div20 Reserved Div6
1 Div24 Div30 Div8 Div10
00
Div2
Div8
CPU
Bit1,0
01 10
Div3 Div4
Div8 Div8
11
Div6
Div8
7.14 Register 13: ( Default : 3Fh )
BIT
AFFECTED PIN/
FUNCTION NAME(S)
PWD
7 EN_MN_PROG
0
6 Reserved
5 Reserved
4 Reserved
0
1
1
FUNCTION DESCRIPTION
TYPE
0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N
value
The equation is
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be
clear. Then the frequency will be decided by
hardware default FS<4:0> or desired
frequency select SAF_FREQ[4:0] depend on
EN_SAFE_FREQ (Reg0 – bit0).
Reserved
R/W
Reserved
R/W
- 12 -
Publication Release Date: Feb 2006
Revision 0.6










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