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PDF ( 数据手册 , 数据表 ) FX-101-CFF-A4P2

零件编号 FX-101-CFF-A4P2
描述 Frequency Translator
制造商 ETC
LOGO ETC LOGO 


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FX-101-CFF-A4P2 数据手册, 描述, 功能
Product Data Sheet
FX-101
Frequency Translator
Features
• Output frequencies up to 77.760 MHz
• Jitter Generation OC-192 compliant
• Jitter transfer per GR-253-CORE
• Single 5.0 or 3.3 Vdc supply
• Locked to specified Input frequency, e.g. 8 kHz
• 1" X 0.8" X 0.2", Surface Mount (FR4base)
• Optional CMOS or PECL Output
Applications
• SONET / SDH / ATM
• DWDM / FDM
• DSL-PON Interconnects
• FEC (Forward Error Correction)
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 •Web: www.vectron.com







FX-101-CFF-A4P2 pdf, 数据表
FX-101 Frequency Translator
FAQ’s
Q: What are the different input frequencies that are available?
A: The FX-100 series is able to handle any input frequency between 8 kHz and 170 MHz.
(A list of standard frequencies is available on pages 9 and 10.)
Q: How many different input frequencies can a specific FX-101 accept?
A: Each FX-101 can be programmed to accept up to 4 different frequencies.
Q: If there is only one input pin, how can your unit accept 4 different frequencies?
A: The user is required to supply a multiplexer which would switch between the different input
frequencies.The multiplexers’ select pins would need to be sync’d to the select pins of the FX-101.
(See The Typical Application illustrated on page 6.)
Q: Can a single FX-101 handle an application for 4 input frequencies of 8 kHz, 19.44, 38.88 and 77.76 MHz
all being translated to 77.76 MHz, with the 77.76 MHz input being LvPECL and the others HCMOS?
A: Yes; since the FX-101 AC couples the input signal, this combination can be supported.
Q: What is the lock time for the FX-101?
A: The exact lock time will depend on the specific input frequency. It should be noted that in all cases
the lock time will be significantly less than 1 second.
Q: I asked for a FX-101-DFC-A2S2 with 19.44 and 155.52 MHz for the input frequencies and was given a
Source Control Drawing (SCD) number of FX-101-DFC-S5999 Why was a new number assigned?
A: Whenever there are multiple input frequencies, we need to assign a SCD for the unit so that we can
include a table indicating what the logic levels need to be on pins 12 and 13 to control the unit per
the correct input frequency.
Q: What are the exact jitter transfer specs that the FX-101 series meets?
A: The FX-101 meets the stringent jitter transfer specs in GR-253 for Category II jitter (Section 5.6.2.1.2)
for all OC-n levels.
Q: Does the output frequency need to be 77.76 MHz?
A: No, the output frequency can be any frequency between 1.544 MHz and 77.76 MHz.
(A list of standard frequencies is available on pages 9 and 10.)
Q: What type of noise on the supply line can the FX-101 suppress?
A: The FX-101 is designed to clean up noise on the Input Clock Signal, it is not designed to clean up
noisy power supplies. If excessive noise is present on the supply line it may degrade the output
jitter performance. Additional external filtering may be required. Please consult with your power
supply vendor on the best way to filter noise on your supply line.
Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • Web:www.vectron.com














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