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PDF ( 数据手册 , 数据表 ) ADSP-21487

零件编号 ADSP-21487
描述 SHARC Processor
制造商 Analog Devices
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ADSP-21487 数据手册, 描述, 功能
SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 450 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Qualified for automotive applications
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD
64-BIT
Core Bus
PMD
64-BIT
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
PERIPHERAL BUS
32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
FFT
FIR
IIR
DTCP/
MTM
SPEP BUS
CORE PWM
WDT FLAGS 3-0
EP
AMI
SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADSP-21487 pdf, 数据表
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
• Arbitration logic to coordinate core and DMA transfers
between internal and external memory over the external
port.
Non-SDRAM external memory address space is shown in
Table 5.
Table 5. External Memory for Non-SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
6M
8M
8M
8M
Address Range
0x0020 0000–0x007F FFFF
0x0400 0000–0x047F FFFF
0x0800 0000–0x087F FFFF
0x0C00 0000–0x0C7F FFFF
External Port
The external port provides a high performance, glueless inter-
face to a wide variety of industry-standard memory devices. The
external port, available on the 176-lead LQFP, may be used to
interface to synchronous and/or asynchronous memory devices
through the use of its separate internal memory controllers. The
first is an SDRAM controller for connection of industry-stan-
dard synchronous DRAM devices while the second is an
asynchronous memory controller intended to interface to a
variety of memory devices. Four memory select pins enable up
to four separate devices to coexist, supporting any desired com-
bination of synchronous and asynchronous device types.
Asynchronous Memory Controller
The asynchronous memory controller provides a configurable
interface for up to four separate banks of memory or I/O
devices. Each bank can be independently programmed with dif-
ferent timing parameters, enabling connection to a wide variety
of memory devices including SRAM, flash, and EPROM, as well
as I/O devices that interface with standard memory control
lines. Bank 0 occupies a 6M word window and banks 1, 2, and 3
occupy a 8M word window in the processor’s address space but,
if not fully populated, these windows are not made contiguous
by the memory controller logic.
SDRAM Controller
The SDRAM controller provides an interface of up to four sepa-
rate banks of industry-standard SDRAM devices at speeds up to
fSDCLK. Fully compliant with the SDRAM standard, each bank has
its own memory select line (MS0–MS3), and can be configured
to contain between 4M bytes and 256M bytes of memory.
SDRAM external memory address space is shown in Table 6.
NOTE: this feature is not available on the ADSP-21486 model.
Table 6. External Memory for SDRAM Addresses
Bank
Bank 0
Bank 1
Bank 2
Bank 3
Size in
Words
62M
64M
64M
64M
Address Range
0x0020 0000–0x03FF FFFF
0x0400 0000–0x07FF FFFF
0x0800 0000–0x0BFF FFFF
0x0C00 0000–0x0FFF FFFF
A set of programmable timing parameters is available to config-
ure the SDRAM banks to support slower memory devices. Note
that 32-bit wide devices are not supported on the SDRAM and
AMI interfaces.
The SDRAM controller address, data, clock, and control pins
can drive loads up to distributed 30 pF. For larger memory sys-
tems, the SDRAM controller external buffer timing should be
selected and external buffering should be provided so that the
load on the SDRAM controller pins does not exceed 30 pF.
Note that the external memory bank addresses shown are for
normal-word (32-bit) accesses. If 48-bit instructions as well as
32-bit data are both placed in the same external memory bank,
care must be taken while mapping them to avoid overlap.
SIMD Access to External Memory
The SDRAM controller on the processor supports SIMD access
on the 64-bit EPD (external port data bus) which allows access
to the complementary registers on the PEy unit in the normal
word space (NW). This removes the need to explicitly access the
complimentary registers when the data is in external SDRAM
memory.
VISA and ISA Access to External Memory
The SDRAM controller on the ADSP-2148x processors sup-
ports VISA code operation which reduces the memory load
since the VISA instructions are compressed. Moreover, bus
fetching is reduced because, in the best case, one 48-bit fetch
contains three valid instructions. Code execution from the tra-
ditional ISA operation is also supported. Note that code
execution is only supported from bank 0 regardless of
VISA/ISA. Table 7 shows the address ranges for instruction
fetch in each mode.
Table 7. External Bank 0 Instruction Fetch
Size in
Access Type Words
ISA (NW)
4M
VISA (SW) 10M
Address Range
0x0020 0000–0x005F FFFF
0x0060 0000–0x00FF FFFF
Pulse-Width Modulation
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).
The entire PWM module has four groups of four PWM outputs
generating 16 PWM outputs in total. Each PWM group pro-
duces two pairs of PWM signals on the four PWM outputs.
Rev. C | Page 8 of 68 | June 2015







ADSP-21487 equivalent, schematic
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
Table 11. Pin Descriptions (Continued)
Name
MLBCLK1
MLBDAT1
MLBSIG1
MLBDO1
MLBSO1
Type
I
State
During/
After Reset
I/O/T in 3
pin mode. I
in 5 pin
mode.
I/O/T in 3
pin mode. I
in 5 pin
mode
O/T
High-Z
High-Z
High-Z
O/T High-Z
Description
Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-
nized to the MOST network and provides the timing for the entire MLB interface at
49.152 MHz at FS=48 kHz. When the MLB controller is not used, this pin should be
grounded.
Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and
is received by all other MLB devices including the MLB controller. The MLBDAT line
carries the actual data. In 5-pin MLB mode, this pin is an input only. When the MLB
controller is not used, this pin should be grounded.
Media Local Bus Signal. This is a multiplexed signal which carries the Channel/Address
generated by the MLB Controller, as well as the Command and RxStatus bytes from
MLB devices. In 5-pin mode, this pin is input only. When the MLB controller is not used,
this pin should be grounded.
Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB mode.
This serves as the output data pin in 5-pin mode. When the MLB controller is not used,
this pin should be connected to ground.
Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode. This serves as the output signal pin in 5-pin mode. When the MLB controller is
not used, this pin should be connected to ground.
TDI I (ipu)
Test Data Input (JTAG). Provides serial data for the boundary scan logic.
TDO
O/T
High-Z
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TMS I (ipu)
Test Mode Select (JTAG). Used to control the test state machine.
TCK I
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the device.
TRST
I (ipu)
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the processor.
EMU
O (O/D, ipu) High-Z
Emulation Status. Must be connected to the ADSP-2148x Analog Devices DSP Tools
product line of JTAG emulators target board connector only.
The following symbols appear in the Type column of this table: A = asynchronous, I = input, O = output, S = synchronous, A/D = active drive,
O/D = open drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic
levels. To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot
be enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 kΩ–63 kΩ. The
range of an ipd resistor can be between 31 kΩ–85kΩ. The three-state voltage of ipu pads will not reach to the full VDD_EXT level; at typical
conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, all pins are LVTTL compliant with the exception of the thermal diode pins.
Rev. C | Page 16 of 68 | June 2015










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