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PDF ( 数据手册 , 数据表 ) 74HC05-Q100

零件编号 74HC05-Q100
描述 Hex inverter
制造商 NXP Semiconductors
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74HC05-Q100 数据手册, 描述, 功能
74HC05-Q100
Hex inverter with open-drain outputs
Rev. 1 — 9 July 2012
Product data sheet
1. General description
The 74HC05-Q100 is a high-speed Si-gate CMOS device that complies with JEDEC
standard no. 7A.
The 74HC05-Q100 contains six inverters. The outputs of the 74HC05-Q100 are
open-drain and can be connected to other open-drain outputs to implement active-LOW
wired-OR or active-HIGH wired-AND functions. The open-drain outputs require pull-up
resistors to perform correctly.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide operating voltage 2.0 V to 6.0 V
Input levels:
For 74HC05-Q100: CMOS level
Latch-up performance exceeds 100 mA per JESD 78 Class II level A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )
Multiple package options







74HC05-Q100 pdf, 数据表
NXP Semiconductors
74HC05-Q100
Hex inverter with open-drain outputs
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
tW
VM
tr
tf
VM
VI
G
VCC
DUT
RT
VO
VCC
RL S1
CL
open
001aad983
Fig 7.
Test data is given in Table 9.
Definitions test circuit:
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
RL = Load resistance.
Test circuit for measuring switching times
Table 9.
Input
VI
VCC
Test data
tr, tf
6 ns
Load
CL
50 pF
RL
1 k
S1 position
tPZL, tPLZ
VCC
74HC05_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 July 2012
© NXP B.V. 2012. All rights reserved.
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