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PDF ( 数据手册 , 数据表 ) JS28F512P33TFA

零件编号 JS28F512P33TFA
描述 Micron Parallel NOR Flash Embedded Memory
制造商 MICRON
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JS28F512P33TFA 数据手册, 描述, 功能
512Mb, 1Gb, 2Gb: P33-65nm
Features
Micron Parallel NOR Flash Embedded
Memory (P33-65nm)
JS28F512P33BFD, JS28F512P33TFA, JS28F512P33EFA
PC28F512P33BFD, PC28F512P33TFA, PC28F512P33EFA
JS28F00AP33BFA, JS28F00AP33TFA, JS28F00AP33EFA
PC28F00AP33BFA, PC28F00AP33TFA, PC28F00AP33EFA,
PC28F00BP33EFA
Features
• High performance
• Easy BGA package features
– 95ns initial access for 512Mb, 1Gb Easy BGA
– 100ns initial access for 2Gb Easy BGA
– 25ns 16-word asychronous page read mode
– 52 MHz (Easy BGA) with zero WAIT states and
17ns clock-to-data output synchronous burst
read mode
– 4-, 8-, 16-, and continuous word options for burst
mode
• TSOP package features
– 105ns initial access for 512Mb, 1Gb TSOP
• Both Easy BGA and TSOP package features
– Buffered enhanced factory programming (BEFP)
at 2 MB/s (TYP) using a 512-word buffer
– 3.0V buffered programming at 1.46 MB/s (TYP)
using a 512-word buffer
• Architecture
– MLC: highest density at lowest cost
– Symmetrically blocked architecture (512Mb, 1Gb,
2Gb)
– Asymmetrically blocked architecture (512Mb,
1Gb); four 32KB parameter blocks: top or bottom
configuration
– 128KB main blocks
– Blank check to verify an erased block
• Voltage and power
– VCC (core) voltage: 2.3–3.6V
– VCCQ (I/O) voltage: 2.3–3.6V
– Standy current: 70µA (TYP) for 512Mb; 75µA
(TYP) for 1Gb
– 52 MHz continuous synchronous read current:
21mA (TYP), 24mA (MAX)
• Security
– One-time programmable register: 64 OTP bits,
programmed with unique information from Mi-
cron; 2112 OTP bits available for customer pro-
gramming
– Absolute write protection: VPP = VSS
– Power-transition erase/program lockout
– Individual zero-latency block locking
– Individual block lock-down
– Password access
• Software
25μs (TYP) program suspend
25μs (TYP) erase suspend
– Flash Data Integrator optimized
– Basic command set and extended function Inter-
face (EFI) command set compatible
– Common flash interface
• Density and Packaging
– 56-lead TSOP package (512Mb, 1Gb)
– 64-ball Easy BGA package (512Mb, 1Gb, 2Gb)
– 16-bit wide data bus
• Quality and reliabilty
– JESD47 compliant
– Operating temperature: –40°C to +85°C
– Minimum 100,000 ERASE cycles per block
– 65nm process technology
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.







JS28F512P33TFA pdf, 数据表
512Mb, 1Gb, 2Gb: P33-65nm
Virtual Chip Enable Description
Virtual Chip Enable Description
The 2Gb device employs a virtual chip enable feature, which combines two 1Gb die
with a common chip enable, CE# for Easy BGA packages. The maximum address bit is
then used to select between the die pair with CE# asserted. When CE# is asserted and
the maximum address bit is LOW, the lower parameter die is selected; when CE# is as-
serted and the maximum address bit is HIGH, the upper parameter die is selected.
Table 3: Virtual Chip Enable Truth Table for Easy BGA Packages
Die Selected
Lower parameter die
Upper parameter die
CE#
L
L
A[MAX]
L
H
Figure 1: Easy BGA Block Diagram
Easy BGA (Dual Die) Top/Bottom
Parameter Configuration
CE#
WP#
OE#
WE#
CLK
ADV#
A[MAX:1]
Top Parameter Die
Bottom Parameter Die
RST#
VCC
VPP
VCCQ
VSS
DQ[15:0]
WAIT
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
8 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.







JS28F512P33TFA equivalent, schematic
512Mb, 1Gb, 2Gb: P33-65nm
Signal Descriptions
Table 4: TSOP and Easy BGA Signal Descriptions (Continued)
Symbol
WAIT
VCC
VCCQ
VSS
RFU
DU
NC
Type
Output
Power
Power
Power
Name and Function
Wait: Indicates data valid in synchronous array or non-array burst reads. Read configura-
tion register bit 10 (RCR.10, WT) determines its polarity when asserted. This signal's active
output is VOL or VOH when CE# and OE# are VIL. WAIT is High-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, this signal indicates invalid data when as-
serted and valid data when de-asserted.
• In asynchronous page mode, and all write modes, this signal is de-asserted.
Device core power supply: Core (logic) source voltage. Writes to the array are inhibited
when VCC VLKO. Operations at invalid VCC voltages should not be attempted.
Output power supply: Output-driver source voltage.
Ground: Connect to system ground. Do not float any VSS connection.
Reserved for future use: Reserved by Micron for future device functionality and en-
hancement. These should be treated in the same way as a DU signal.
Do not use: Do not connect to any other signal, or power supply; must be left floating.
No connect: No internal connection; can be driven or floated.
PDF: 09005aef845667b8
p33_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. C 12/13 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.










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