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PDF ( 数据手册 , 数据表 ) A93C46

零件编号 A93C46
描述 1K (128 x 8 OR 64 x 16) THREE-WIRE SERIAL EEPROM
制造商 AiT Semiconductor
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A93C46 数据手册, 描述, 功能
AiT Semiconductor Inc.
www.ait-ic.com
 
A93C46
THREE-WIRE SERIAL EEPROM
1K (128 X 8 OR 64 X 16)
DESCRIPTION
The A93C46 provides 1024 bits of serial
electrically erasable programmable read only
memory (EEPROM) organized as 64 words of
16 bits each, when the ORG pin is connected to
VCC and 128 words of 8 bits each when it is tied
to ground. The A93C46 is enabled through the
Chip Select pin (CS), and accessed via a 3-wire
serial interface consisting of Data Input (DI),
Data Output (DO), and Shift Clock (SK). Upon
receiving a Read instruction at DI, the address is
decoded and the data is clocked out serially on
the data output pin DO. The WRITE cycle is
completely self-timed and no separate erase
cycle is required before write. The Write cycle is
only enabled when it is in the Erase/Write
Enable state. When CS is brought “high”
following the initiation of a write cycle, the DO
pin outputs the Ready/Busy status.
The A93C46 is available in SOP8 and TSSOP8
Package.
FEATURES
Three-Wire Serial Interface
VCC=1.8V to 5.5V
Self-Timed Write Cycle (5ms Max)
2 MHz Rate(5V) Compatibility
1 Million Write Cycles Guaranteed
Data Retention>100 Years
Available in SOP8 and TSSOP8 Package 
 
ORDERING INFORMATION
Package Type Part Number
A93C46M8R
SOP8
A93C46M8U
M8
A93C46M8VR
A93C46M8VU
A93C46TMX8R
TSSOP8
A93C46TMX8U
TMX8
A93C46TMX8VR
A93C46TMX8VU
R: Tape & Reel
Note
U: Tube
V: Halogen free Package
AiT provides all RoHS products
suffix “ V “ means Halogen free Package
REV1.2
 
- FEB 2010 RELEASED, FEB 2012 DATED -
-1-







A93C46 pdf, 数据表
AiT Semiconductor Inc.
www.ait-ic.com
 
A93C46
THREE-WIRE SERIAL EEPROM
1K (128 X 8 OR 64 X 16)
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the
logical “1”state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The
DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250ns (TCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part
is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the
specified memory location. The self-timed programming cycle, tWP, starts after the last bit of data is received
at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of 250ns (TCS). A logic “0” at DO indicates that programming is still in progress.
A logic “1” indicates that the memory location at the specified address has been written with the data pattern
contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be
obtained if the CS is brought high after the end of the self timed programming cycle, TWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1”
state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is
brought high after being kept low for a minimum of 250ns (TCS). The ERAL instruction is valid only at VCC =
5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns
specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after
being kept low for a minimum of 250ns (TCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable
(EWDS) instruction disables all programming modes and should be executed after all programming
operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions
and can be executed at any time.
REV1.2
 
- FEB 2010 RELEASED, FEB 2012 DATED -
-8-














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