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PDF ( 数据手册 , 数据表 ) 3400

零件编号 3400
描述 5 Series Chipset
制造商 Intel
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3400 数据手册, 描述, 功能
Intel® 5 Series Chipset and
Intel® 3400 Series Chipset
Datasheet
January 2012
Document Number: 322169-004







3400 pdf, 数据表
5.22
5.23
5.24
5.25
5.26
5.27
5.28
5.21.2.9 Case for Considerations ........................................................ 250
Intel® High Definition Audio Overview (D27:F0)................................................... 252
5.22.1 Intel® High Definition Audio Docking (Mobile Only) ................................ 252
5.22.1.1 Dock Sequence ................................................................... 252
5.22.1.2 Exiting D3/CRST# when Docked ............................................ 253
5.22.1.3 Cold Boot/Resume from S3 When Docked ............................... 254
5.22.1.4 Undock Sequence ................................................................ 254
5.22.1.5 Normal Undock.................................................................... 254
5.22.1.6 Surprise Undock .................................................................. 255
5.22.1.7 Interaction Between Dock/Undock and Power Management
States ................................................................................ 255
5.22.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# .......... 255
Intel® Active Management Technology 6.0 (Intel® AMT) ....................................... 256
5.23.1 Intel® AMT6.x and ASF 2.0 Features .................................................... 257
5.23.2 Intel® AMT Requirements ................................................................... 257
Serial Peripheral Interface (SPI) ........................................................................ 258
5.24.1 SPI Supported Feature Overview ......................................................... 258
5.24.1.1 Non-Descriptor Mode ........................................................... 258
5.24.1.2 Descriptor Mode .................................................................. 258
5.24.1.3 Device Partitioning............................................................... 260
5.24.2 Flash Descriptor ................................................................................ 260
5.24.2.1 Descriptor Master Region ...................................................... 262
5.24.3 Flash Access ..................................................................................... 263
5.24.3.1 Direct Access Security .......................................................... 263
5.24.3.2 Register Access Security ....................................................... 263
5.24.4 Serial Flash Device Compatibility Requirements ..................................... 264
5.24.4.1 PCH SPI Based BIOS Requirements ........................................ 264
5.24.4.2 Integrated LAN Firmware SPI Flash Requirements .................... 264
5.24.4.3 Intel® Management Engine Firmware SPI Flash Requirements ... 265
5.24.4.4 Hardware Sequencing Requirements ...................................... 265
5.24.5 Multiple Page Write Usage Model.......................................................... 266
5.24.5.1 Soft Flash Protection ............................................................ 266
5.24.5.2 BIOS Range Write Protection................................................. 267
5.24.5.3 SMI# Based Global Write Protection ....................................... 267
5.24.6 Flash Device Configurations ................................................................ 267
5.24.7 SPI Flash Device Recommended Pinout................................................. 267
5.24.8 Serial Flash Device Package ................................................................ 268
5.24.8.1 Common Footprint Usage Model ............................................ 268
5.24.8.2 Serial Flash Device Package Recommendations ........................ 268
Intel® Quiet System Technology (Intel® QST) (Desktop Only) ............................... 269
5.25.1 PWM Outputs .................................................................................... 269
5.25.2 TACH Inputs ..................................................................................... 269
Feature Capability Mechanism ........................................................................... 269
PCH Display Interfaces and Intel® Flexible Display Interconnect............................. 270
5.27.1 Analog Display Interface Characteristics................................................ 270
5.27.1.1 Integrated RAMDAC ............................................................. 271
5.27.1.2 DDC (Display Data Channel) ................................................. 271
5.27.2 Digital Display Interfaces .................................................................... 271
5.27.2.1 LVDS (Mobile only) .............................................................. 271
5.27.2.2 LVDS Pair States ................................................................. 272
5.27.2.3 Single Channel versus Dual Channel Mode .............................. 273
5.27.2.4 Panel Power Sequencing ....................................................... 273
5.27.2.5 LVDS DDC .......................................................................... 274
5.27.2.6 High Definition Multimedia Interface....................................... 274
5.27.2.7 Digital Video Interface (DVI) ................................................. 275
5.27.2.8 Display Port* ...................................................................... 275
5.27.2.9 Embedded DisplayPort.......................................................... 275
5.27.2.10 DisplayPort Aux Channel....................................................... 276
5.27.2.11 DisplayPort Hot-Plug Detect (HPD) ......................................... 276
5.27.2.12 Integrated Audio over HDMI and DisplayPort ........................... 276
5.27.2.13 Serial Digital Video Out (SDVO) ............................................. 276
5.27.2.14 Control Bus......................................................................... 277
5.27.3 Mapping of Digital Display Interface Signals .......................................... 278
5.27.4 Multiple Display Configurations ............................................................ 279
5.27.5 High-bandwidth Digital Content Protection (HDCP) ................................. 279
5.27.6 Intel® Flexible Display Interconnect ..................................................... 280
Intel® Virtualization Technology ........................................................................ 280
8 Datasheet







3400 equivalent, schematic
14.2
14.3
14.4
14.1.39 FLRCID—FLR Capability ID Register (SATA–D31:F2) ............................... 594
14.1.40 FLRCLV—FLR Capability Length and Version
Register (SATA–D31:F2).................................................................... 595
14.1.41 FLRC—FLR Control Register (SATA–D31:F2) .......................................... 595
14.1.42 ATC—APM Trapping Control Register (SATA–D31:F2).............................. 596
14.1.43 ATS—APM Trapping Status Register (SATA–D31:F2)............................... 596
14.1.44 SP Scratch Pad Register (SATA–D31:F2) ............................................... 596
14.1.45 BFCS—BIST FIS Control/Status Register (SATA–D31:F2) ........................ 597
14.1.46 BFTD1—BIST FIS Transmit Data1 Register (SATA–D31:F2) ..................... 599
14.1.47 BFTD2—BIST FIS Transmit Data2 Register (SATA–D31:F2) ..................... 599
Bus Master IDE I/O Registers (D31:F2)............................................................... 600
14.2.1 BMIC[P,S]—Bus Master IDE Command Register (D31:F2) ....................... 601
14.2.2 BMIS[P,S]—Bus Master IDE Status Register (D31:F2)............................. 602
14.2.3 BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register (D31:F2).............................................................................. 603
14.2.4 AIR—AHCI Index Register (D31:F2) ..................................................... 603
14.2.5 AIDR—AHCI Index Data Register (D31:F2)............................................ 603
Serial ATA Index/Data Pair Superset Registers..................................................... 604
14.3.1 SINDX—Serial ATA Index Register (D31:F2) .......................................... 604
14.3.2 SDATA—Serial ATA Data Register (D31:F2) ........................................... 605
14.3.2.1 PxSSTS—Serial ATA Status Register (D31:F2) ......................... 605
14.3.2.2 PxSCTL—Serial ATA Control Register (D31:F2) ........................ 606
14.3.2.3 PxSERR—Serial ATA Error Register (D31:F2) ........................... 607
AHCI Registers (D31:F2) .................................................................................. 608
14.4.1 AHCI Generic Host Control Registers (D31:F2)....................................... 609
14.4.1.1 CAP—Host Capabilities Register (D31:F2) ............................... 609
14.4.1.2 GHC—Global PCH Control Register (D31:F2)............................ 611
14.4.1.3 IS—Interrupt Status Register (D31:F2)................................... 612
14.4.1.4 PI—Ports Implemented Register (D31:F2)............................... 613
14.4.1.5 VS—AHCI Version Register (D31:F2) ...................................... 614
14.4.1.6 CCC_CTL—Command Completion Coalescing Control
Register (D31:F2)................................................................ 614
14.4.1.7 CCC_Ports—Command Completion Coalescing Ports
Register (D31:F2)................................................................ 615
14.4.1.8 EM_LOC—Enclosure Management Location Register (D31:F2) .... 615
14.4.1.9 EM_CTRL—Enclosure Management Control Register (D31:F2) .... 616
14.4.1.10 VS—AHCI Version Register (D31:F2) ...................................... 617
14.4.1.11 VSP—Vendor Specific Register (D31:F2) ................................. 617
14.4.1.12 RSTF—Intel® RST Feature Capabilities Register ....................... 617
14.4.2 Port Registers (D31:F2)...................................................................... 619
14.4.2.1 PxCLB—Port [5:0] Command List Base Address Register
(D31:F2) ............................................................................ 623
14.4.2.2 PxCLBU—Port [5:0] Command List Base Address Upper
32-Bits Register (D31:F2) ..................................................... 623
14.4.2.3 PxFB—Port [5:0] FIS Base Address Register (D31:F2) .............. 624
14.4.2.4 PxFBU—Port [5:0] FIS Base Address Upper 32-Bits
Register (D31:F2)................................................................ 624
14.4.2.5 PxIS—Port [5:0] Interrupt Status Register (D31:F2)................. 625
14.4.2.6 PxIE—Port [5:0] Interrupt Enable Register (D31:F2) ................ 626
14.4.2.7 PxCMD—Port [5:0] Command Register (D31:F2)...................... 628
14.4.2.8 PxTFD—Port [5:0] Task File Data Register (D31:F2) ................. 631
14.4.2.9 PxSIG—Port [5:0] Signature Register (D31:F2) ....................... 631
14.4.2.10 PxSSTS—Port [5:0] Serial ATA Status Register (D31:F2) .......... 632
14.4.2.11 PxSCTL—Port [5:0] Serial ATA Control Register (D31:F2).......... 633
14.4.2.12 PxSERR—Port [5:0] Serial ATA Error Register (D31:F2) ............ 634
14.4.2.13 PxSACT—Port [5:0] Serial ATA Active Register (D31:F2) ........... 635
14.4.2.14 PxCI—Port [5:0] Command Issue Register (D31:F2) ................ 636
15 SATA Controller Registers (D31:F5) ....................................................................... 637
15.1 PCI Configuration Registers (SATA–D31:F5) ........................................................ 637
15.1.1 VID—Vendor Identification Register (SATA—D31:F5) .............................. 638
15.1.2 DID—Device Identification Register (SATA—D31:F5) .............................. 638
15.1.3 PCICMD—PCI Command Register (SATA–D31:F5) .................................. 639
15.1.4 PCISTS—PCI Status Register (SATA–D31:F5) ........................................ 640
15.1.5 RID—Revision Identification Register (SATA—D31:F5) ............................ 640
15.1.6 PI—Programming Interface Register (SATA–D31:F5) .............................. 641
15.1.7 SCC—Sub Class Code Register (SATA–D31:F5) ...................................... 641
16 Datasheet










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