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PDF ( 数据手册 , 数据表 ) AS4C16M16D1-5BIN

零件编号 AS4C16M16D1-5BIN
描述 16M x 16 bit DDR Synchronous DRAM
制造商 Alliance Semiconductor
LOGO Alliance Semiconductor LOGO 


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AS4C16M16D1-5BIN 数据手册, 描述, 功能
AS4C16M16D1
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Advanced (Rev. 1.1, Sep. /2011)
Features
Fast clock rate: 200MHz
Differential Clock CK & CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Overview
The AS4C16M16D1 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256 Mbits.
It is internally configured as a quad 4M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK). Data outputs occur
at both rising edges of CK and CK .d Read and write
accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command
which is then followed by a Read or Write command. The
AS4C16M16D1 provides programmable Read or Write
burst lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition, AS4C16M16D1 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory band-width, result in a device particularly well
suited to high performance main memory and graphics
applications.
Table 1.Ordering Information
Part Number
Clock Data Rate Package Temperature Temp Range
AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial 0 ~ 70°C
AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII Industrial -40 ~ 85°C
AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial 0 ~ 70°C
AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA Industrial -40 ~ 85°C
T: indicates TSOP II package
B: indicates TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.







AS4C16M16D1-5BIN pdf, 数据表
AS4C16M16D1
Addressing Mode Select Field (A3)
The Addressing Mode can be one of two modes, either Interleave Mode or Sequential Mode. Both Sequential
Mode and Interleave Mode support burst length of 2, 4 and 8.
Table 6. Addressing Mode
A3 Addressing Mode
0 Sequential
1 Interleave
Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Table 7. Burst Address ordering
Burst Length
2
4
8
Start Address
A2 A1
XX
XX
X0
X0
X1
X1
00
00
01
01
10
10
11
11
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sequential
0, 1
1, 0
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
Interleave
0, 1
1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
CAS Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value
satisfying the following formula must be programmed into this field.tCAC(min) CAS Latency X tCK
Table 8. CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
Reserved
2.5 clocks
Reserved
Alliance Memory, lnc. Confidential
8
Rev. 1.1
Sep. /2011







AS4C16M16D1-5BIN equivalent, schematic
Timing Waveforms
Figure 4. Activating a Specific Row in a Specific Bank
CK
CK
CKE
CS
HIGH
RAS
CAS
WE
Address
RA
BA0,1
BA
RA=Row Address
BA=Bank Address
Don’t Care
AS4C16M16D1
Alliance Memory, lnc. Confidential
16
Rev. 1.1
Sep. /2011










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