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PDF ( 数据手册 , 数据表 ) 87332I-01

零件编号 87332I-01
描述 ECL/LVPECL Clock Generator
制造商 IDT
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87332I-01 数据手册, 描述, 功能
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
87332I-01
DATA SHEET
GENERAL DESCRIPTION
The 87332I-01 is a high performance ÷2 Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator. The CLK, nCLK pair can accept
most standard differential input levels The 87332I-01 is characterized
to operate from either a 2.5V or a 3.3V power supply. Guaranteed
output and part-to-part skew characteristics make the 87332I-01
ideal for those clock distribution applications demanding well defined
performance and repeatability.
FEATURES
• One ÷2 differential 2.5V/3.3V LVPECL / ECL output
• One CLK, nCLK input pair
• CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 500MHz
• Maximum input frequency: 1GHz
• Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Part-to-part skew: 400ps (maximum)
• Propagation delay: 1.6ns (maximum)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -2.375V to -3.8V
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
CLK
nCLK
÷2
Q
nQ
MR
PIN ASSIGNMENT
MR
CLK
nCLK
nc
1
2
3
4
8 Vcc
7Q
6 nQ
5 VEE
87332I-01
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
87332AMI-01 REVISION C 2/12/15
1 ©2015 Integrated Device Technology, Inc.







87332I-01 pdf, 数据表
87332AMI-01 DATA SHEET
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 5A to 5F show interface
examples for the CLK/nCLK input driven by the most common driv-
er types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm
the driver termination requirements. For example in Figure 5A, the
input termination applies for IDT open emitter LVHSTL drivers. If
you are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
LVPECL
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 5A. CLK/nCLK INPUT DRIVEN BY AN IDT OPEN
EMITTER LVHSTL DRIVER
FIGURE 5B. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 5C. CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL
DRIVER
FIGURE 5D. CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
FIGURE 5E. CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER FIGURE 5F. CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER
÷2, Differential-to-2.5V/3.3V
ECL/LVPECL Clock Generator
8
REVISION C 2/12/15














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