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零件编号 | TCN75 | ||
描述 | 2-Wire Serial Temperature Sensor and Thermal Monitor | ||
制造商 | Microchip | ||
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1 Page
TCN75
2-Wire Serial Temperature Sensor and Thermal Monitor
Features:
• Solid-State Temperature Sensing:
0.5°C Accuracy (Typ.)
• Operates from -55°C to +125°C
• Operating Supply Range: 2.7V to 5.5V
• Programmable Trip Point and Hysteresis with
Power-up Defaults
• Standard 2-Wire Serial Interface
• Thermal Event Alarm Output Functions as
Interrupt or Comparator/Thermostat Output
• Up to 8 TCN75s may Share the Same Bus
• Shutdown Mode for Low Standby Power
Consumption
• 5V Tolerant I/O at VDD = 3V
• Low Power:
- 250 μA (Typ.) Operating
- 1 μA (Typ.) Shutdown Mode
• 8-Pin SOIC and MSOP Packaging
Applications:
• Thermal Protection for High-Performance CPUs
• Solid-State Thermometer
• Fire/Heat Alarms
• Thermal Management in Electronic Systems:
- Computers
- Telecom Racks
- Power Supplies/UPS/Amplifiers
• Copiers/Office Electronics
• Consumer Electronics
• Process Control
Package Type
SOIC
SDA 1
SCL 2
INT/CMPTR 3
GND 4
8 VDD
7 A0
TCN75MOA
6 A1
5 A2
MSOP
SDA 1
SCL 2
INT/CMPTR 3
GND 4
8 VDD
7 A0
TCN75MUA
6 A1
5 A2
General Description:
The TCN75 is a serially programmable temperature
sensor that notifies the host controller when ambient
temperature exceeds a user programmed set point.
Hysteresis is also programmable. The INT/CMPTR
output is programmable as either a simple comparator
for thermostat operation or as a temperature event
interrupt. Communication with the TCN75 is
accomplished via a two-wire bus that is compatible with
industry standard protocols. This permits reading the
current temperature, programming the set point and
hysteresis, and configuring the device.
The TCN75 powers up in Comparator mode with a
default set point of 80°C with 5°C hysteresis. Defaults
allow independent operation as a stand-alone
thermostat. A shutdown command may be sent via the
2-wire bus to activate the low-power Standby mode.
Address selection inputs allow up to eight TCN75s to
share the same 2-wire bus for multizone monitoring.
All registers can be read by the host and the INT/
CMPTR output’s polarity is user programmable. Both
polled and interrupt driven systems are easily
accommodated. Small physical size, low installed cost,
and ease-of-use make the TCN75 an ideal choice for
implementing sophisticated system management
schemes.
© 2006 Microchip Technology Inc.
DS21490C-page 1
TCN75
4.0 SHUTDOWN MODE
When the appropriate bit is set in the configuration reg-
ister (CONFIG) the TCN75 enters its low-power Shut-
down mode (IDD = 1 μA, typical) and the temperature-
to-digital conversion process is halted. The TCN75’s
bus interface remains active and TEMP, TSET, and
THYST may be read from and written to. Transitions on
SDA or SCL due to external bus activity may increase
the standby power consumption. If the TCN75 is in
Interrupt mode, the state of INT/CMPTR will be reset
upon entering Shutdown mode.
4.1 Fault Queue
To lessen the probability of spurious activation of INT/
CMPTR the TCN75 may be programmed to filter out
transient events. This is done by programming the
desired value into the Fault Queue. Logic inside the
TCN75 will prevent the device from triggering INT/
CMPTR unless the programmed number of sequential
temperature-to-digital conversions yield the same
qualitative result. In other words, the value reported in
TEMP must remain above TSET or below THYST for the
consecutive number of cycles programmed in the Fault
Queue. Up to a six-cycle “filter” may be selected. See
Section 5.0 “Register Set and Programmer’s
ModeL”, Register Set and Programmer’s Model.
4.2 Serial Port Operation
The Serial Clock input (SCL) and bidirectional data port
(SDA) form a 2-wire bidirectional serial port for pro-
gramming and interrogating the TCN75. The following
table indicates TCN75 conventions that are used in this
bus scheme.
TABLE 4-1: SERIAL BUS CONVENTIONS
Term
Explanation
Transmitter
Receiver
Master
Slave
Start
Stop
ACK
NOT Busy
Data Valid
The device sending data to the bus.
The device receiving data from the bus.
The device which controls the bus: initiating
transfers (Start), generating the clock, and
terminating transfers (Stop).
The device addressed by the master.
A unique condition signaling the beginning of
a transfer indicated by SDA falling (High –
Low) while SCL is high.
A unique condition signaling the end of a
transfer indicated by SDA rising (Low – High)
while SCL is high.
A Receiver acknowledges the receipt of each
byte with this unique condition. The Receiver
drives SDA low during SCL high of the ACK
clock-pulse. The Master provides the clock
pulse for the ACK cycle.
When the bus is idle, both SDA & SCL will
remain high.
The state of SDA must remain stable during
the High period of SCL in order for a data bit
to be considered valid. SDA only changes
state while SCL is low during normal data
transfers. (See Start and Stop conditions).
All transfers take place under control of a host, usually
a CPU or microcontroller, acting as the Master, which
provides the clock signal for all transfers. The TCN75
always operates as a Slave. This serial protocol is
illustrated in Figure 5-1. All data transfers have two
phases; and all bytes are transferred MSB first.
Accesses are initiated by a Start condition, followed by
a device address byte and one or more data bytes. The
device address byte includes a Read/Write selection
bit. Each access must be terminated by a Stop condi-
tion. A convention called Acknowledge (ACK) confirms
receipt of each byte. Note that SDA can change only
during periods when SCL is LOW (SDA changes while
SCL is HIGH are reserved for Start and Stop condi-
tions).
4.3 Start Condition (Start)
The TCN75 continuously monitors the SDA and SCL
lines for a Start condition (a HIGH-to-LOW transition of
SDA while SCL is HIGH), and will not respond until this
condition is met.
DS21490C-page 8
© 2006 Microchip Technology Inc.
TCN75
NOTES:
DS21490C-page 16
© 2006 Microchip Technology Inc.
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页数 | 20 页 | ||
下载 | [ TCN75.PDF 数据手册 ] |
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