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PDF ( 数据手册 , 数据表 ) PAS6371LT

零件编号 PAS6371LT
描述 CMOS VGA DIGITAL IMAGE SENSOR
制造商 Pixart Imaging
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PAS6371LT 数据手册, 描述, 功能
PAS6371LT Specification
PAS6371LT CMOS VGA DIGITAL IMAGE SENSOR
General Description
The PAS6371LT is a highly integrated CMOS active-pixel image sensor that has a VGA YUV output of 640
x 480 pixels. It embedded the new FinePixel™ sensor technology to perform the excellent image quality.
PAS6371LT outputs YUV/YCbCr 4:2:2 or RGB565/555/444 data through a parallel data bus. It is available in
29-pin CSP.
Features
ƒ Resolution: 640 x 480 pixels
ƒ Bayer-RGB color filter array
ƒ Output format (8-bit):
z YUV/YCbCr 4:2:2 (VGA,
QVGA … )
z RGB565/555/444 (VGA, QVGA … )
ƒ On-chip 10-bit pipelined A/D converter
ƒ On-chip 2-stage background compensation
DAC
ƒ Continuous variable frame time & exposure
time
ƒ I2CTM Interface
ƒ Flash light timing
ƒ Support 1.8V~3.3V I/O power
ƒ 10uA low power-down dissipation
(VDD-A = VDD-IO = 2.8V, VDD-C = 1.8V)
ƒ Automatic Background Compensation
ƒ AEC & AGC function
ƒ DSP function:
z AWB
z Gamma
z Color matrix
z Sharpness
z De-noise
z Color saturation
z Defect compensation
z Lens shading compensation
ƒ WOI & Sub-sampling
ƒ Critical Register table backward compatible
with PAS6311
Key Specification
Resolution
Analog
Power
I/O
Core
Pixel Size
Lens Chief Ray Angle
Frame rate
Max. System clock
Max. Pixel clock
Sensitivity
Color filter
Exposure Time
Scan Mode
S/N Ratio
Dynamic range
Package
640 (H) x 480 (V)
2.5V ~ 3.0V
1.8V ~ 3.3V
1.8V
4.5µmx4.5µm
28degree
30fps, VGA YUV mode
48MHz
24MHz, VGA YUV mode
2.1V/(Lux*Sec)
RGB Bayer Pattern
~ Frame time to Line time
Progressive
41dB
60dB
29-pin CSP
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
1
2008/04/09







PAS6371LT pdf, 数据表
PixArt Imaging Inc.
PAS6371LT
CMOS Image Sensor IC
Data Transfer Format
Master transmits data to salve ( write cycle )
z S : Start.
z A : Acknowledge by salve.
z P : Stop.
z RW : The LSB of 1ST byte to decide whether current cycle is read or write cycle. RW = 1 –
Read cycle, RW = 0 – Write cycle.
z SUBADDRESS : The address values of PAS6371LT internal control registers. ( Please refer
to PAS6371LT register description )
During write cycle, the master generates start condition and then places the 1st byte data that are
combined slave address ( 7 bits ) with a read / write control bit to SDA line. After slave ( PAS6371LT )
issues acknowledgment, the master places 2nd byte ( Sub Address ) data on SDA line. Again follow the
PAS6371LT acknowledgment, the master places the 8 bits data on SDA line and transmit to PAS6371LT
control register ( address was assigned by 2nd byte ). After PAS6371LT issues acknowledgment, the
master can generate a stop condition to end of this write cycle. In the condition of multi-byte write, the
PAS6371LT sub-address is automatically increment after each DATA byte transferred. The data and A
cycles is repeat until last byte write. Every control registers value inside PAS6371LT can be programming
via this way.
Slave transmits data to master ( read cycle )
z The sub-address was taken from previous write cycle.
z The sub-address is automatically increment after each byte read.
z Am : Acknowledge by master.
z Note there is no acknowledgment from master after last byte read.
During read cycle, the master generates start condition and then place the 1st byte data that are combined
slave address ( 7 bits ) with a read / write control bit to SDA line. After issue acknowledgment, 8 bits
DATA was also placed on SDA line by PAS6371LT. The 8 bits data was read from PAS6371LT internal
control register that address was assigned by previous write cycle. Follow the master acknowledgment,
the PAS6371LT place the next 8 bits data ( address is increment automatically ) on SDA line and then
transmit to master serially. The DATA and Am cycles is repeat until the last byte read. After last byte read,
Am is no longer generated by master but instead by keep SDA line high. The slave ( PAS6371LT ) must
releases SDA line to master to generate STOP condition.
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
8
2008/04/09







PAS6371LT equivalent, schematic
PixArt Imaging Inc.
PAS6371LT
[3:2] RGB565_mode[1:0]
[4] RGB565_En
[5] RGB555_En
[6] RGB444_En
C1 [0] Vsync_INV
[1] Hsync_INV
E3 - EE [7:0] Reserved
CMOS Image Sensor IC
0x00
0x00
0x00
0x00
0x00
0x00
xx
RGB565_mode
RGB565 Enable
(ISP2_UpdateFlag=1, update )
RGB555 Enable
(ISP2_UpdateFlag=1, update )
RGB444 Enable
(ISP2_UpdateFlag=1, update )
Vsync inverse
Hsync inverse
Reserved
All rights strictly reserved any portion in this paper shall not be reproduced, copied or transformed to any other forms without permission.
PixArt Imaging Inc.
V1.1,
16
2008/04/09










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