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PDF ( 数据手册 , 数据表 ) WM8235

零件编号 WM8235
描述 70MSPS 9-Channel AFE
制造商 Wolfson Microelectronics
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WM8235 数据手册, 描述, 功能
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WM8235
70MSPS 9-Channel AFE with Sensor Timing Generation and
LVDS/CMOS Data Output
DESCRIPTION
The WM8235 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 23MSPS.
The device has nine analogue signal processing channels
each of which contains Reset Level Clamping, Correlated
Double Sampling (also Sample and Hold), Programmable
Gain, Automatic Gain Control (AGC) and Offset adjust
functions.
The output from each of these channels is time multiplexed,
in pairs, into three high-speed 16-bit Analogue to Digital
Converters. The digital data is available in a variety of
output formats via the flexible data port.
The WM8235 has a user selectable LVDS or CMOS output
architecture.
An internal 8-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Clamping to clamp CCD signals. An
external reference level may also be supplied. ADC
references are generated internally, ensuring optimum
performance from the device.
A programmable automatic Black-Level Calibration function
is available to adjust the DC offset of the output data.
The WM8235 features a sensor timing clock generator for
both CCD and CIS sensors. The clock generator can accept
a slow or fast reference clock input and also has a flexible
timing adjustment function for output timing clocks to allow
use of many different sensors.
FEATURES
70MSPS conversion rate
16 bit ADC resolution
Current consumption – 390mA
3.3V single supply operation
Sample and hold /correlated double sampling
Programmable offset adjust (8-bit resolution)
Flexible clamp timing
Pixel clamp / line clamp mode
Programmable clamp voltage
Programmable CIS/CCD timing generator
Internally generated voltage references
Compliant for Spread Spectrum Clock
LVDS/CMOS output options
LVDS 5pair 490MHz 35-bit data
CMOS 90MHz output maximum
Complete on chip clock generator. MCLK 5MHz to 23MHz
Internal timing adjustment
Automatic Gain Control
Automatic Black Level Calibration
56-lead QFN package 7mm x 7mm
Serial control interface
APPLICATIONS
Digital copiers
USB2.0 compatible scanners
Multi-function peripherals
High-speed CCD/CIS sensor interface
WOLFSON MICROELECTRONICS plc
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Product Brief, February 2012, Rev 3.0
Copyright 2012 Wolfson Microelectronics plc.







WM8235 pdf, 数据表
WM8235
Product Brief
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = LDOVDD = DBVDD = 3.3V , AGND = LDOGND = DBGND= 0V, TA = 25C, MCLK= 23.3MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate per channel
5
Full-scale input voltage range
ADCFS=0, Max Gain
(see Note 1)
ADCFS=0, Min Gain
ADCFS=1, Max Gain
ADCFS=1, Min Gain
Input signal limits (see Note 2)
VIN
SF_INP=0
SF_INP=1
AGND-0.3
AGND
Input capacitance
Full-scale transition error
CIN Inputs to AGND
Gain = 0dB;
AGAIN[4:0] = 02(hex)
DGAIN[11:0] = 6AB(hex)
Zero-scale transition error
Gain = 0dB;
AGAIN[4:0] = 02(hex)
DGAIN[11:0] = 6AB(hex)
Differential non-linearity
DNL
10-bit
Integral non-linearity (pk-pk/2)
INL
10-bit
Channel to channel gain matching Min Gain
Max Gain
Output noise
Unity Gain
(Unused channels grounded)
Channel to channel crosstalk
10-bit
TYP
0.12
2.0
0.18
3.0
10
20
20
0.5
1
5
15
0.3
+/-0.5
MAX
UNIT
23.3
AVDD+0.3
AGND+1.2
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
V
pF
mV
mV
LSB
LSB
%
%
LSB rms
LSB
Programmable Gain Amplifier
Total Resolution (Ga + Gd)
Analogue Gain
Max gain, each channel (Ga)
Min gain, each channel (Ga)
Digital Gain
Max gain, each channel (Gd)
Min gain, each channel (Gd)
Max gain, each channel
(Ga + Gd)
Min gain, each channel
(Ga + Gd)
Analogue to Digital Converter
Resolution
Speed
GT
Ga
Ga MAX
Ga MIN
Gd
Gd MAX
Gd MIN
GTMAX
GTMIN
AGAIN[4:0] = 1F(hex)
AGAIN[4:0] = 0(hex)
DGAIN[11:0] = FFF(hex)
DGAIN[11:0] = 400 (hex)
AGAIN[4:0] = 1F(hex)
DGAIN[11:0] = FFF(hex)
AGAIN[4:0] = 0(hex)
DGAIN[11:0] = 400 (hex)
12
0.6 + 0.3 * AGAIN[4:0]
9.9
0.6
DGAIN[11:0] / 211
2
0.5
19.8
0.3
bits
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
16 bits
70 MSPS
Notes:
1. Full-scale input voltage denotes the differential input signal amplitude (VIN-VRLC in non-CDS mode, VIN-RESET
level in CDS mode) that can be gained to match the ADC full-scale input range.
2. Input signal limits are the limits within which each input voltage and VRLC reference must lie.
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Product Brief, Rev 3.0, February 2012
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