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PDF ( 数据手册 , 数据表 ) XE167GM

零件编号 XE167GM
描述 16-Bit Single-Chip Real Time Signal Controller
制造商 Infineon
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XE167GM 数据手册, 描述, 功能
16-Bit
Architecture
XE167FM, XE167GM,
XE167HM, XE167KM
16-Bit Single-Chip Real Time Signal
Controller
XE166 Family Derivatives / Base Line
Data Sheet
V2.0 2009-03
Microcontrollers







XE167GM pdf, 数据表
XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family Derivatives / Base Line
Summary of Features
– Up to four capture/compare units for flexible PWM signal generation (CCU6x)
– Two Synchronizable A/D Converters with up to 24 channels, 10-bit resolution,
conversion time below 1 μs, optional data preprocessing (data reduction, range
check), broken wire detection
– Up to 6 serial interface channels to be used as UART, LIN, high-speed
synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s),
IIS interface
– On-chip MultiCAN interface (Rev. 2.0B active) with up to 128 message objects
(Full CAN/Basic CAN) on up to 6 CAN nodes and gateway functionality
– On-chip system timer and on-chip real time clock
• Up to 12 Mbytes external address space for code and data
– Programmable external bus characteristics for different address ranges
– Multiplexed or demultiplexed external address/data buses
– Selectable address bus width
– 16-bit or 8-bit data bus width
– Five programmable chip-select signals
– Hold- and hold-acknowledge bus arbitration support
• Single power supply from 3.0 V to 5.5 V
• Programmable watchdog timer and oscillator watchdog
• Up to 119 general purpose I/O lines
• On-chip bootstrap loaders
• Supported by a full range of development tools including C compilers, macro-
assembler packages, emulators, evaluation boards, HLL debuggers, simulators,
logic analyzer disassemblers, programming boards
• On-chip debug support via Device Access Port (DAP) or JTAG interface
• 144-pin Green LQFP package, 0.5 mm (19.7 mil) pitch
Data Sheet
8 V2.0, 2009-03







XE167GM equivalent, schematic
XE167FM, XE167GM, XE167HM, XE167KM
XE166 Family Derivatives / Base Line
General Device Information
Table 4
Pin Definitions and Functions (cont’d)
Pin Symbol
Ctrl. Type Function
10 P8.2
O0 / I St/B Bit 2 of Port 8, General Purpose Input/Output
CCU60_CC6 O1 St/B CCU60 Channel 2 Output
2
TxDC1
O2 St/B CAN Node 1 Transmit Data Output
U1C1_DOUT O3 St/B USIC1 Channel 1 Shift Data output
CCU60_CC6 I
2INB
St/B CCU60 Channel 2 Input
11 P7.1
O0 / I St/B Bit 1 of Port 7, General Purpose Input/Output
EXTCLK
O1 St/B Programmable Clock Signal Output
TXDC4
O2 St/B CAN Node 4 Transmit Data Output
CCU62_CTR I
APA
St/B CCU62 Emergency Trap Input
BRKIN_C
I
St/B OCDS Break Signal Input
12 P7.4
O0 / I St/B Bit 4 of Port 7, General Purpose Input/Output
EMUX2
O1 St/B External Analog MUX Control Output 2 (ADC1)
U0C1_DOUT O2 St/B USIC0 Channel 1 Shift Data Output
U0C1_SCLK O3 St/B USIC0 Channel 1 Shift Clock Output
OUT
CCU62_CCP I
OS2A
St/B CCU62 Position Input 2
TCK_C
I St/B DAP0/JTAG Clock Input
U0C0_DX0D I
St/B USIC0 Channel 0 Shift Data Input
U0C1_DX1E I
St/B USIC0 Channel 1 Shift Clock Input
13 P8.1
O0 / I St/B Bit 1 of Port 8, General Purpose Input/Output
CCU60_CC6 O1 St/B CCU60 Channel 1 Output
1
CCU60_CC6 I
1INB
St/B CCU60 Channel 1 Input
RxDC1F
I St/B CAN Node 1 Receive Data Input
Data Sheet
16 V2.0, 2009-03










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