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PDF ( 数据手册 , 数据表 ) WT588D-U

零件编号 WT588D-U
描述 Voice Module
制造商 WT
LOGO WT LOGO 


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WT588D-U 数据手册, 描述, 功能
The Instructions of WT588D -U Voice Module
CATALOG UE







WT588D-U pdf, 数据表
8、 control mode
WT588D-U
http://VOICE-CHIP.RU
8.1、 Buttons Control Mode
Pins can directly trigger a function of chip to work. Each pin of the trigger can be set indivi dually.
Shockproof time of this mode time is about 10ms. There are 15 trigger ways. Including trigger Impulse
Repetition , trigger pluse Without Repetition , invalidation keys, no cycle Level , Recycled Level ,
Non-Maintained Cycle Level, Non -Cycle for The Last Tone ,Non -Cycle for The Next Tone , Cycle for The
Last Tone , Cycle for The Next Tone, Volume +, Volume -, play / pause, stop, play / stop, etc. see the
following trigger timing diagram. For more details, see the following chart:
8.1.1、 Trigger Impulse Repetition
Pluse
Vo i c e
Busy signal
Note: Negative trigger pulse. When the I / O port inspects the falling edge (for example, the I / O port click
short-circuit to GND), Voice will be broadcast .If do that again when the Voice are sti ll playing, the voice
will be interrupted and replay. Therefore, it will be replay as long as has falling edge signal.
8.1.2、 Trigger Impluse Without Repetition
Pluse
Vo i c e
Busy signal
Note: Negative trigger pulse. When the I / O port inspects the fall ing edge (for example, the I / O port click
short-circuit to GND), Voice will be broadcast. If do that again when the voice are still playing , the voice
will not be interrupted and continue to broadcast. To be valid unless the voice at an end and inspects the
falling edge.
-8 -







WT588D-U equivalent, schematic
5ms
CS
CLK 300us
WT588D-U
http://VOICE-CHIP.RU
DATA
VOICE
BUSY
D0 D1 D2 D3 D4 D5 D6 D7
20ms
Description: WT588D-U voice module begins to send data signals after current is switched on and wairt
17ms.
8.3.5、 Models of Procedure
Master SCM PIC16F54 System frequency 4MHz
Send threelines(unsigned char addr)
cs=0;
delay1ms(5);
/* Chip select signal keep low level 2ms */
for(i=0;i<8;i++)
scl=0;
if(addr & 1)sda=1;
else sda=0;
addr>>=1;
delay1us(300);
/* Clock cycle 300us */
scl=1;
delay1us(300);
cs=1;
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