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PDF ( 数据手册 , 数据表 ) IS43TR16256AL

零件编号 IS43TR16256AL
描述 4Gb DDR3 SDRAM
制造商 ISSI
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IS43TR16256AL 数据手册, 描述, 功能
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
512Mx8, 256Mx16 4Gb DDR3 SDRAM
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
High speed data transfer rates with system
frequency up to 1066 MHz
8 internal banks for concurrent operation
8n-Bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
SEPTEMBER 2016
Refresh Interval:
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)
Write Leveling
Up to 200 MHz in DLL off mode
Operating temperature:
Commercial (TC = 0°C to +95°C)
Industrial (TC = -40°C to +95°C)
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
OPTIONS
Configuration:
512Mx8
256Mx16
Package:
96-ball BGA (9mm x 13mm) for x16
78-ball BGA (9mm x 10.5mm) for x8
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge
Addressing
BL switch on the fly
512Mx8
A0-A15
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
256Mx16
A0-A14
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
15H
125K
107M
JEDEC Speed Grade DDR3-1333H DDR3-1600K DDR3-1866M
CL-nRCD-nRP
9-9-9
11-11-11
13-13-13
tRCD,tRP(min)
13.5
13.75
13.91
Note:Faster speed options are backward compatible to slower speed options.
093N
DDR3-2133N
14-14-14
13.09
Units
tCK
ns
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
1







IS43TR16256AL pdf, 数据表
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3 SDRAM is now ready for normal operation.
CK,CK#
VDD,VDDQ
Ta Tb
((
)( ()
))
((
))
Tc Td Te Tf Tg Th Ti Tj Tk
(( (( (( (( (( (( (( ((
)( () )( () )( () )( () )( () )( () )( () )( ()
)) )) )) )) )) )) )) ))
tCKSRX
((
))
((
))
(( ((
)) ))
((
))
(( (( ((
)) )) ))
RESET#
CKE
T=200µS
((
))
Tmin=10nS
((
)( ()
))
T=5(0(0µS
))
tIS
((
))
((
)( ()
))
(( ((
)) ))
((
))
(( (( ((
)( () )( () )( ()
)) )) ))
(( ((
)) ))
(( ((
)( () )( ()
)) ))
tDLLK
((
))
((
)( () Valid
))
CMMAND
BA
ODT
((
)( ()
))
((
)( ()
))
((
)( ()
))
tXPR
tIS
tMRD
tMRD
tMRD
tMOD
tZQinit
(( (( (( (( (( (( (( ((
)( () 1) )( () MRD )( () MRD )( () MRD )( () MRD )( () ZQCL )( () 1) )( () Valid
)) )) )) )) )) )) )) ))
((
(( (( (( ((
(( (( ((
)( () )( () MR2 )( () MR3 )( () MR1 )( () MR0 )( () )( () )( () Valid
))
)) )) )) ))
)) )) ))
tIS tIS
(( ((
(( ((
)( () Stat)(i()c LOW in case RTT_Nom is enabled at time Tg, otherwise static HIG)( H() or LOW )( () Valid
)) ))
)) ))
RTT
((
((
((
(( ((
((
(( ((
))
))
))
)) ))
))
)) ))
Note1. From time point Td” until “Tk” NOP or DES commands must be
applied between MRS and ZQCL commands.
( ( Time
) ) Break
Figure2.1.1 Reset and Initialization Sequence at Power-on Ramping
((
))
DON’T
CARE
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
8







IS43TR16256AL equivalent, schematic
IS43/46TR16256A, IS43/46TR16256AL,
IS43/46TR85120A, IS43/46TR85120AL
2.3.4.4 Dynamic ODT (Rtt_WR)
DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing
an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT setings. In Write leveling mode, only
RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
2.3.5 Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#, RAS#,
CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the below.
BA2 BA1 BA0
011
A15-A13
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0* 1 MPR MPR Loc Mode Register 3
MRP Operation
A2 MPR
0 Normal operation *3
1 Dataflow from MPR
MPR Address
A1 A0
00
01
10
11
MPR location
Predefined pattern *2
RFU
RFU
RFU
BA1 BA0
00
01
10
11
MR Select
MR0
MR1
MR2
MR3
* 1 : A3 - A15 must be programmed to 0 during MRS.
* 2 : The predefined pattern will be used for read synchronization.
* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
Figure 2.3.5 MR3 Definition
2.3.5.1 Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To
enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the
MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any
subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD
or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0).
Power down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The
RESET function is supported during MPR enable mode.
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. The
basic concept of the MPR is shown in Figure 2.3.5.1.
Integrated Silicon Solution, Inc. www.issi.com
Rev. G2
07/28/2016
16










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