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PDF ( 数据手册 , 数据表 ) ATmega16U4

零件编号 ATmega16U4
描述 8-bit Microcontroller
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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ATmega16U4 数据手册, 描述, 功能
ATmega16U4/ATmega32U4
8-bit Microcontroller with 16/32K bytes of ISP Flash and
USB Controller
DATASHEET
Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-Chip 2-cycle Multiplier
Non-volatile Program and Data Memories
– 16/32KB of In-System Self-Programmable Flash
– 1.25/2.5KB Internal SRAM
– 512Bytes/1KB Internal EEPROM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/ 100 years at 25C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Parts using external XTAL clock are pre-programed with a default USB bootloader
– Programming Lock for Software Security
JTAG (IEEE® std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Complies fully with Universal Serial Bus Specification Rev 2.0
– Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s
– Endpoint 0 for Control Transfers: up to 64-bytes
– Six Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independent 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– CPU Reset possible on USB Bus Reset detection
– 48MHz from PLL for Full-speed Bus Operation
– USB Bus Connection/Disconnection on Microcontroller Request
– Crystal-less operation for Low Speed mode
Peripheral Features
– On-chip PLL for USB and High Speed Timer: 32 up to 96MHz operation
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
Atmel-7766I-USB-ATmega16U4/32U4-Datasheet_072015







ATmega16U4 pdf, 数据表
3. About
3.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of other AVR
microcontrollers manufactured on the same process technology. Min. and Max. values will be available after the
device is characterized.
3.2 Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
3.3 Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Confirm with the C compiler documentation for more details.
These code examples assume that the part specific header file is included before compilation. For I/O registers
located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with
instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC",
"SBR", and "CBR".
3.4 Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1PPM over
20 years at 85°C or 100 years at 25°C.
8 ATmega16U4/32U4 [DATASHEET]
Atmel-7766I-USB-ATmega16U4/32U4-Datasheet_072015







ATmega16U4 equivalent, schematic
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will
be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following
example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
;
store SREG value
cli ; disable interrupts during
timed sequence
sbi EECR, EEMPE
;
start EEPROM write
sbi EECR, EEPE
out SREG, r16
;
restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;
store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
/*
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any
pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending
interrupt(s) */
4.8.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock
cycles the program vector address for the actual interrupt handling routine is executed. During these five clock
cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt
routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in
sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in
addition to the start-up time from the selected sleep mode.
ATmega16U4/32U4 [DATASHEET]
Atmel-7766I-USB-ATmega16U4/32U4-Datasheet_072015
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