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PDF ( 数据手册 , 数据表 ) APL5930

零件编号 APL5930
描述 Ultra Low Dropout (0.23V Typical) Linear Regulator
制造商 ANPEC
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APL5930 数据手册, 描述, 功能
APL5930
3A, Ultra Low Dropout (0.23V Typical) Linear Regulator
Features
General Description
Compatible with APL5913
The APL5930 is a 3A ultra low dropout linear regulator.
Ultra Low Dropout
The IC needs two supply voltages, one is a control voltage
- 0.23V(typical) at 3A Output Current
Low ESR Output Capacitor (Multi-layer
Chip Capacitors (MLCC)) Applicable
0.8V Reference Voltage
High Output Accuracy
(V ) for the control circuitry, the other is a main supply
CNTL
voltage (VIN) for power conversion, to reduce power dissi-
pation and provide extremely low dropout voltage.
The APL5930 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages on
VCNTL and VIN pins to prevent erroneous operations.
- ±1.5% over Line, Load, and Temperature Range The functions of thermal shutdown and current-limit pro-
Fast Transient Response
tect the device against thermal and current over-loads. A
Adjustable Output Voltage
POK indicates the output voltage status with a delay time
Power-On-Reset Monitoring on Both VCNTL and set internally. It can control other converter for power
VIN Pins
sequence. The APL5930 can be enabled by other power
Internal Soft-Start
systems. Pulling and holding the EN voltage below 0.4V
Current-Limit and Short Current-Limit Protections shuts off the output.
The APL5930 is available in a SOP-8P package which
Thermal Shutdown with Hysteresis
features small size as SOP-8 and an Exposed Pad to
Open-Drain VOUT Voltage Indicator (POK)
reduce the junction-to-case resistance to extend power
Low Shutdown Quiescent Current (<30 µA)
range of applications.
Shutdown/Enable Control Function
Simple SOP-8P Package with Exposed Pad
Applications
Lead Free and Green Devices Available
Front Side Bus VTT (1.2V/3A)
(RoHS Compliant)
Note Book PC Applications
Motherboard Applications
Pin Configuration
Simplified Application Circuit
GND 1
FB 2
VOUT 3
VOUT 4
8 EN
7 POK
6 VCNTL
5 VIN
SOP-8P (Top View)
= Exposed Pad
(connected to VIN plane for better heat dissipation)
POK
EN
Enable
VCNTL
POK VIN
VOUT
APL5930
EN FB
GND
VCNTL
VIN
VOUT
Optional
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
1
www.anpec.com.tw







APL5930 pdf, 数据表
APL5930
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=1.8V, VCNTL=5V, VOUT=1.2V, TA= 25oC
unless otherwise specified.
Shutdown
Enable
VEN
1
2
3
4
VPOK
VOUT
IOUT
COUT=10µF, CIN=10µF, RL=0.4
CH1: VEN, 5V/Div, DC
CH2: VOUT, 1V/Div, DC
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
TIME: 2µs/Div
VEN
1
VOUT
2
3
IOUT
4
VPOK
COUT=10µF, CIN=10µF, RL=0.4
CH1: VEN, 5V/Div, DC
CH2: VOUT, 0.5V/Div, DC
CH3: VPOK, 5V/Div, DC
CH4: IOUT, 2A/Div, DC
TIME: 0.5ms/Div
Pin Description
PIN
NO. NAME
1 GND
2 FB
34
VOUT
5 VIN
6 VCNTL
7 POK
8
Exposed
Pad
EN
-
FUNCTION
Ground pin of the circuitry. All voltage levels are measured with respect to this pin.
Voltage Feedback Pin. Connecting this pin to an external resistor divider receives the feedback voltage
of the regulator.
Output pin of the regulator. Connecting this pin to load and output capacitors (10µF at least) is required
for stability and improving transient response. The output voltage is programmed by the resistor-divider
connected to FB pin. The VOUT can provide 3A (max.) load current to loads. During shutdown, the
output voltage is quickly discharged by an internal pull-low MOSFET.
Main supply input pin for voltage conversions. A decoupling capacitor (≥10µF recommended) is usually
connected near this pin to filter the voltage noise and improve transient response. The voltage on this
pin is monitored for Power-On-Reset purpose.
Bias voltage input pin for internal control circuitry. Connect this pin to a voltage source (+5V
recommended). A decoupling capacitor (1µF typical) is usually connected near this pin to filter the
voltage noise. The voltage at this pin is monitored for Power-On-Reset purpose.
Power-OK signal output pin. This pin is an open-drain output used to indicate the status of output
voltage by sensing FB voltage. This pin is pulled low when output voltage is not within the Power-OK
voltage window.
Active-high enable control pin. Applying and holding the voltage on this pin below the enable voltage
threshold shuts down the output. When re-enabled, the IC undergoes a new soft-start process. When
leave this pin open, an internal pull-up current (5µA typical) pulls the EN voltage and enables the
regulator.
Connect this pad to system VIN plane for good thermal conductivity.
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
8
www.anpec.com.tw







APL5930 equivalent, schematic
APL5930
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time (tP)** within 5°C of the specified
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax)
3 °C/second max.
183 °C
60-150 seconds
See Classification Temp in table 1
20** seconds
6 °C/second max.
3°C/second max.
217 °C
60-150 seconds
See Classification Temp in table 2
30** seconds
6 °C/second max.
Time 25°C to peak temperature
6 minutes max.
8 minutes max.
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Volume mm3
Thickness
<350
<2.5 mm
2.5 mm
235 °C
220 °C
Volume mm3
350
220 °C
220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Volume mm3
Thickness
<350
<1.6 mm
260 °C
1.6 mm – 2.5 mm
260 °C
2.5 mm
250 °C
Volume mm3
350-2000
260 °C
250 °C
245 °C
Volume mm3
>2000
260 °C
245 °C
245 °C
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ 125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM 2KV
VMM 200V
10ms, 1tr 100mA
Copyright © ANPEC Electronics Corp.
Rev. A.4 - Sep., 2009
16
www.anpec.com.tw










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