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PDF ( 数据手册 , 数据表 ) AR7242

零件编号 AR7242
描述 A High Performance And Cost-Effective Network Processor
制造商 Atheros
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AR7242 数据手册, 描述, 功能
Data Sheet
April 2011
AR7242: A High Performance And Cost-Effective Network
Processor
General Description
The Atheros AR7242 is a high performance
and cost effective network processor for access
point, router, and gateway applications. It
includes a MIPS 24Kc processor, PCI Express
1.1 host interface, integrated 10/100 Mbps
Fast Ethernet MAC/PHY, one RGMII port,
one USB 2.0 MAC/PHY, and external memory
interface for serial Flash, DDR1 or DDR2
interface, an I2S audio interface, a high-speed
UART, and GPIOs that can be used for LED
controls or other general purpose interface
configurations.
The AR7242 is a memory-centric architecture
including various DMA controlled interfaces
that access the DDR memory.
The AR7242 network processor, when paired
with the AR928x/AR938x/AR939x single
chip 802.11n MAC/BB/Radio family,
provides the best-in-class WLAN solution
capable of supporting 802.11b/g/n standards.
Features
Integrated MIPS 24 K 32-bit processor
operating at up to 400 MHz
64 K instruction cache and 32 K data cache
Integrated 10/100 802.3 Ethernet LAN port
and one RGMII port
16-bit DDR1 or DDR2 memory interface
supporting up to 400 M transfers per
second
An external serial Flash memory interface
(maximum 16 MBytes)
One USB 2.0 controller with built-in MAC/
PHY
High-speed UART and multiple GPIO pins
for general purpose I/O or LED control
A single lane PCI Express 1.1 interface that
can be used for interfacing to the AR928x/
AR938x/AR939x single chip 802.11n
MAC/BB/Radio
JTAG port support for processor core
14 mm x 14 mm 128-pin LQFP lead-free
package
System Block Diagram
© 2010-2011 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, ETHOS®, IQUE®, No
New Wires®, Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-
Nav®, Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, ROCm™,
amp™, Install N Go™, Simpli-Fi™, SmartLink™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered
trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1







AR7242 pdf, 数据表
PRELIMINARY
Parameters (HCCPARAMS) ... 134
4.11.15 Device Interface Version Number
(DCIVERSION) ......................... 134
4.11.16 Device Control Capability
Parameters (DCCPARAMS) .... 134
4.11.17 USB Command (USBCMD) ... 135
4.11.18 USB Status (USBSTS) .............. 137
4.11.19 USB Interrupt Enable (USBINTR)
139
4.11.20 USB Frame Index (FRINDEX) 141
4.11.21 Frame List Base Address
(PERIODICLISTBASE) ............. 142
4.11.22 USB Device Address
(DEVICEADDR) ....................... 142
4.11.23 Next Asynchronous List Address
(ASYNCLISTADDR) ................ 142
4.11.24 Address at Endpointlist in
Memory
(ENEDPOINTLIST_ADDR) .... 143
4.11.25 TT Status and Control (TTCTRL)
143
4.11.26 Programmable Burst Size
(BURSTSIZE) ............................. 143
4.11.27 Host Tx Pre-Buffer Packet Tuning
(TXFILLTUNING) .................... 144
4.11.28 Endpoint NAK (ENDPTNAK) 145
4.11.29 Endpoint NAK Enable
(ENDPTNAKEN) ...................... 145
4.11.30 Port/Status Control (PORTSC0) .
146
4.11.31 USB Mode (USBMODE) ......... 151
4.11.32 Endpoint Setup Status
(ENDPTSETUPSTAT) .............. 152
4.11.33 Endpoint Initialization
(ENDPTPRIME) ........................ 152
4.11.34 Endpoint De-Initialization
(ENDPTFLUSH) ....................... 153
4.11.35 Endpoint Status
(ENDPTSTATUS) ..................... 153
4.11.36 Endpoint Complete
(ENDPTCOMPLETE) ............... 154
4.11.37 Endpoint Control 0
(ENDPTCTRL0) ........................ 154
4.11.38 Endpoint Control 1
(ENDPTCTRL1) ........................ 155
4.12 Serial Flash Registers .......................... 156
4.12.1 SPI Function Select
(SPI_FUNC_SELECT) .............. 156
4.12.2 SPI Control (SPI_CONTROL) . 156
4.12.3 SPI I/O Control
(SPI_IO_CONTROL) ................ 157
4.12.4 SPI Read Data (SPI_READ_DATA)
157
4.13 Ethernet MAC/PHY Port Registers . 158
4.13.1 Global Control Registers ......... 159
4.13.2 Port Control Registers .............. 170
4.13.3 Statistics Counters .................... 178
5 Electrical Characteristics ..........181
5.1 Absolute Maximum Ratings .............. 181
5.2 Recommended Operating Conditions 181
5.3 General DC Electrical Characteristics 182
5.4 40 MHz Clock Characteristics ............ 184
5.5 Power Consumption ........................... 185
5.6 External Voltage Regulator ................ 186
6 AC Specifications ......................187
6.1 DDR Interface Timing ......................... 187
6.2 Reset Timing ......................................... 188
6.3 SPI Serial Flash Interface Timing ....... 189
6.4 RGMII Characteristics ......................... 190
7 Package Dimensions .................191
8 Ordering Information ...............193
8 • AR7242 Network Processor
8 April 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL







AR7242 equivalent, schematic
PRELIMINARY
Table 1-2. Signal-to-Pin Relationships and Descriptions (continued)
Symbol
Pin Type Description
ERXD0
ERXD1
ERXD2
ERXD3
ERX_EN
ETX_CLK
ETXD0
53 I Receive data
52 I
51 I
49 I
55 I Receive enable
47 O Transmit clock
46 O Transmit data
ETXD1
ETXD2
ETXD3
ETX_EN
44 O
43 O
42 O
48 O Transmit enable
[1]This pin is multiplexed. See Table 1-1.
Symbol
Pin Description
Power
AVDD20
VDD_DDR
VDD12
VDD12CD
VDD25
VDD33
69 Regulated 2.0 V from the AR7242; connect to the external PNP
collector
1, 32, 119
Regulated 2.6 V or 1.8 V output from the AR7242, for DDR1 or
DDR2, respectively; connect to the external PNP collector.
40, 50, 60, 67, 95, 97, 106 Regulated 1.2 V output from the AR7242
12, 23, 113, 128
Regulated 1.28 V output from the AR7242; core voltage of CPU/
DDR blocks, connect pins 12 and 23 to pins 113 and 128
41, 58, 59, 65, 72, 83, 96, Regulated 2.62 V output from the AR7242; I/O voltage
105, 114
71, 117
3.3 V power supply
Ground Pad
Exposed Ground Pad
Tied to GND (see “Package Dimensions” on page 202)
No Connection
NC
45, 68
No connection
16 • AR7242 Network Processor
16 April 2011
Atheros Communications, Inc.
COMPANY CONFIDENTIAL










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