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PDF ( 数据手册 , 数据表 ) AR7100

零件编号 AR7100
描述 High Performance And Cost-Effective Network Processor
制造商 Atheros
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AR7100 数据手册, 描述, 功能
Data Sheet
December 2008
AR7100: A Scalable, High Performance And Cost-Effective
Network Processor Family
General Description
Features
The Atheros AR7100 is a scalable, high
performance and cost effective network
processor family that allows efficient design of
solutions addressing triple play services such
as voice, video and data for home and
enterprise access point, router and gateway
applications. It includes a 32-bit MIPS
processor, PCI host interface, two 802.3
Ethernet MACs with GMII/RGMII/RMII/MII
interface, two USB 2.0 MAC/PHYs, a PCM
interface for glueless SLIC support, external
memory interface for serial Flash and DDR-
SDRAM, a high-speed UART, I2S interface, and
GPIOs that can be used for LED controls.
The AR7100 network processor when paired
with the AR9100 chipset family (AR9160
MAC/baseband processor and AR9106/
AR9104/AR9103/AR9102/AR9101 radios)
provides the best in class WLAN solution
capable of supporting 802.11a/b/g/n
standards.
Integrated MIPS 24K-family processor
300–680 MHz processor frequency:
– AR7130, 300 MHz, Fast Ethernet version
– AR7141, 400 MHz, supports Fast
Ethernet and GB Ethernet
– AR7161, 680 MHz, supports Fast
Ethernet and GB Ethernet
High Performance DDR memory controller
(16- or 32-bit)
Dual IEEE 802.3 Ethernet MAC supporting
10/100/1000 Mbps, full and half duplex
and GMII/RGMII/RMII/MII interfaces
Two-port USB 2.0 Host Controllers with
built-in MAC/PHY
UART for console support
32-bit, 33/66 MHz PCI 2.3 host interface
supporting up to three client devices
IEEE 1149.1 standard test access port and
boundary scan architecture supported
JTAG based debugging of the processor
core supported
13 mm x 13 mm 384 TFBGA lead-free
package
Along with the Atheros AR9100 (MAC/BB
and radio chips) family—Completes an all-
CMOS solution for 802.11a/b/g/n WLANs,
supporting extended range for worldwide
operations
System Block Diagram
2.4/5 GHz
3x
FEM
DDR Controller
and Memory
Interface
AR9103/
AR9106
AR9160
AR9100
40
MHz
Crystal
PCI
Interface
MIPS Processor
AR7100
Ethernet MAC
Ethernet MAC
High Speed UART
USB MAC/PHY
USB MAC/PHY
External Interface
PCM Interface
I2S
Serial Flash/DDR Interface
RGMII Interface
RGMII Interface
UART Interface
USB 2.0 Interface
USB 2.0 Interface
GPIOs/LEDs
SLIC
Audio Interface
© 2000-2008 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super
AG®, Super G®, Total 802.11n®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, the Air
is Cleaner at 5-GHz™, XSPAN™, Wireless Future. Unleashed Now.™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
1







AR7100 pdf, 数据表
Table 1-1. AR7100 Pin Assignments (1–12)
1 2 3 4 5 6 7 8 9 10
A GND
VDD25
VDD25
DDR_DQ_ DDR_DQ_ DDR_DQS_ DDR_DQM_ DDR_DQ_ DDR_DQ_ DDR_DQ_
27 25
3
2 23 22 21
B GND
GND
GND
DDR_DQ_
28
DDR_DQ_
26
DDR_DQ_
24
DDR_DQM_
3
DDR_DQS_2
DDR_VREF
DDR_DQ_
20
C VDD25
VDD25
GND
VDD25
VDD25
VDD25
GND
GND
VDD12
VDD12
D
DDR_DQ_29
DDR_DQ
_30
VDD25
VDD12
VDD12
VDD12
E DDR_DQ_31 DDR_DQ_0 VDD25
F DDR_DQ_1 DDR_DQ_2 GND
G DDR_DQ_4 DDR_DQ_3 GND
H DDR_DQ_5 DDR_VREF VDD25
VDD25
GND
GND
GND
J DDR_DQ_7 DDR_DQ_6 VDD25
VDD25
GND
GND
GND
DDR_DQM_ DDR_DQS
K0
_0
VDD25
VDD25
GND
GND
GND
L
DDR_DQS_1
DDR_DQM
_1
VDD25
VDD25
GND
GND
GND
M DDR_DQ_9 DDR_DQ_8 VDD25
GND
GND
GND
N
DDR_DQ_11
DDR_DQ
_10
VDD25
GND
GND
GND
P
DDR_DQ_13
DDR_DQ
_12
GND
VDD12
GND
GND
GND
R
DDR_CK_N
DDR_DQ
_14
VDD12
VDD12
GND
GND
GND
T
DDR_CK_P
DDR_DQ
_15
VDD12
VDD12
GND
GND
GND
U
DDR_A_12
DDR_VREF
DDR_CKE_
L
VDD12
GND
GND
GND
V DDR_A_11 DDR_BA_0 GND
W DDR_A_9 DDR_A_10 DDR_BA_1
Y DDR_A_8 DDR_A_0 DDR_WE_L
AA
DDR_A_7
DDR_A_1
DDR_CAS_
L
VDD33
VDD33
VDD33
AB DDR_A_6 DDR_A_2 DDR_RAS_L DDR_CS_L UB0VSS33T UBVDD33C USB_ATEST UB1VDD33T VDD33
VDD33
AC DDR_A_5
GND
DDR_A_3 UB0VSS33T UB0VDD33T UBVSS33C
UBXI
UB1VSS33T
UB1VSS33T
UB1VDD33
T
AD GND DDR_A_4 UB0VDD33T USB0_DP USB0_DM USB_REXT UBXO USB1_DM USB1_DP ETH_28
11
DDR_DQ_
19
DDR_DQ_
18
GND
VDD12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD33
ETH_27
ETH_26
ETH_25
12
DDR_DQ_
17
DDR_DQ_
16
VDD25
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ETH_24
ETH_23
ETH_22







AR7100 equivalent, schematic
Table 1-5. Signal-to-Pin Relationships (continued)
Pull-Up/
Signal Name Pin Direction Pull-Down Voltage Description
Ethernet
ETH_0[1]
ETH_1[1]
ETH_2[1]
ETH_3[1]
ETH_4[1]
ETH_5[1]
ETH_6[1]
ETH_7[1]
ETH_8[1]
ETH_9[1]
ETH_10[1]
ETH_11[1]
ETH_12[1]
ETH_13[1]
ETH_14[1]
ETH_15[1]
ETH_16[1]
ETH_17[1]
ETH_18[1]
ETH_19[1]
ETH_20[1]
ETH_21[1]
ETH_22[1]
ETH_23[1]
ETH_24
ETH_25
ETH_26
ETH_27
ETH_28
AD20
AC20
AB20
AD19
AC19
AB19
AD18
AC18
AB18
AD17
AC17
AB17
AD16
AC16
AD15
AC15
AD14
AC14
AB14
AD13
AC13
AB13
AD12
AC12
AB12
AD11
AC11
AB11
AD10
I/O
I/O
I
I
O
I/O
I
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
I/O
O
O
I/O
O
O
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Ethernet Interface signals. Can be configured to
support 2xRGMII or 1xGMII, or 2xRMII or
1xMII+RMII.
[1]This pin is multiplexed. See Table 1-3.
16 • AR7100 Network Processor Family
16 December 2008
Atheros Communications, Inc.
COMPANY CONFIDENTIAL










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