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PDF ( 数据手册 , 数据表 ) GA1086

零件编号 GA1086
描述 11-Output Clock Buffer
制造商 TriQuint Semiconductor
LOGO TriQuint Semiconductor LOGO 


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GA1086 数据手册, 描述, 功能
TRIQUINT
S E M I C O N D U C T O R, I N C .
Figure 1. Block Diagram
FBIN S1 CLK S0 NC NC GND
11 10 9 8 7 6 5
S2 12
VDD 13
Q/2 14
GND 15
FBOUT 16
Q1 17
VDD 18
Control
Logic
Phase
Detector
VCO
Divide
Logic
MUX
Precision
Output
Buffers
4 VDD
3 Q9
2 Q8
1 GND
28 Q7
27 Q6
26 VDD
19 20 21 22 23
GND Q2 Q3 VDD Q4
24 25
Q5 GND
TriQuint’s GA1086 operates from 30 MHz to 67 MHz. This TTL-level clock
buffer chip supports the tight timing requirements of high-performance
microprocessors, with near zero input-to-output delay and very low pin-to-
pin skew. The device offers 10 usable outputs synchronized in phase and
frequency to a periodic clock input signal. One of the ten outputs is a one-
half clock output (CLK ÷ 2). With split termination, the GA1086 can be
used to drive up to nineteen 15 pF loads, as shown in Figure 10.
The tight control over phase and frequency of the output clocks is achieved
with a 400 MHz internal Phase-Locked Loop (PLL). By feeding back one of
the output clocks to FBIN, the on-chip PLL continuously maintains
synchronization between the input clock (CLK) and all ten outputs. Any
drift or gradual variation in the system clock is matched and tracked at the
ten outputs. The GA1086 output buffers are symmetric, each sourcing and
sinking up to 30 mA of drive current. For diagnostic purposes, the device
has a test mode which is used to test the device and associated logic by
single-stepping through the control logic.
GA1086
11-Output
Clock Buffer
Features
Operates from 30 MHz to 67MHz
Pin-to-pin output skew of
250 ps (max)
Period-to-period jitter:
75 ps (typ)
Near-zero propagation delay:
–350 ps ± 500 ps or
–350 ps ± 1000 ps
10 symmetric, TTL-compatible
outputs with 30 mA drive and
rise and fall times of 1.4 ns(max)
28-pin J-lead surface-mount
package
Special test mode
Meets or exceeds Pentium
processor timing requirements
Typical applications include
low-skew clock distribution for:
RISC- or CISC-based systems
Multi-processor systems
High-speed backplanes
The GA1086 is fabricated using TriQuint’s One-Up™ gallium arsenide
technology to achieve precise timing control and to guarantee 100% TTL
compatibility. The output frequency makes this device ideal for clock
generation and distribution in a wide range of high-performance
microprocessor-based systems. Many other CISC- and RISC-based
systems will also benefit from its tight control of skew and delay.
For additional information and latest specifications, see our website: www.triquint.com
1







GA1086 pdf, 数据表
GA1086
If rise times are critical and if overshoots and
undershoots can be tolerated, then unbalanced
termination may be used. Reflections due to
unbalanced termination can cause ringing at the load.
The transmission line lengths, therefore, must be long
enough to cause the ringing to occur only after the
waveform has completely switched to either the LOW
or the HIGH state, (the round trip). The propagation
time of the output signals should be greater than the
switching time for LOW to HIGH or HIGH to LOW.
To double the number of loads (devices) driven by the
GA1086, split termination may be used. Examples of
three types of series termination and the resulting
waveforms, measured between 0.8 V and 2.0 V, are
shown in Figures 9 and 10 for one of the outputs.
Unused outputs must be terminated.
Figure 9. Unbalanced Termination
65
37
FBIN
13
FBOUT
13
Q
CLK
GA1086
37
Qt0
Qt0
65
Qt1
30 pF
Qt1
1.4 ns (max)
1.5 ns (typ)
Figure 10. Split Unbalanced Termination
65
FBIN
13
FBOUT
65
12
13
Q
CLK
GA1086
12
Qt0
15 pF
65
65
Qt0
Qt1
15 pF
Qt1
Qt2
15 pF
Qt2
1.4 ns (max)
1.5 ns (typ)
1.5 ns (typ)
Note: Rise time at Qt1 is measured between 0.8 V and 2.0 V.
8 For additional information and latest specifications, see our website: www.triquint.com














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