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PDF ( 数据手册 , 数据表 ) C8051F305

零件编号 C8051F305
描述 Mixed Signal ISP Flash MCU Family
制造商 Silicon Laboratories
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C8051F305 数据手册, 描述, 功能
C8051F300/1/2/3/4/5
Mixed Signal ISP Flash MCU Family
Analog Peripherals
- 8-Bit ADC ('F300/2 only)
Up to 500 ksps
Up to 8 external inputs
Programmable amplifier gains of 4, 2, 1, & 0.5
VREF from external pin or VDD
Built-in temperature sensor
External conversion start input
- Comparator
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current (<0.5 µA)
On-chip Debug
- On-chip debug circuitry facilitates full speed,
non-intrusive in-system debug (no emulator
required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Complete development kit
Supply Voltage 2.7 to 3.6 V
- Typical operating current: 6.6 mA @ 25 MHz;
14 µA @ 32 kHz
- Typical stop mode current: 0.1 µA
- Temperature range: –40 to +85 °C
High Speed 8051 µc Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 25 MIPS throughput with 25 MHz clock
- Expanded interrupt handler
Memory
- 256 bytes internal data RAM
- Up to 8 kB (‘F300/1/2/3), 4 kB (‘F304), or 2 kB
(‘F305) Flash; 512 bytes are reserved in the 8 kB
devices
Digital Peripherals
- 8 Port I/O; All 5 V tolerant with high sink current
- Hardware enhanced UART and SMBus™ serial
ports
- Three general-purpose 16-bit counter/timers
- 16-bit programmable counter array (PCA) with three
capture/compare modules
- Real time clock mode using PCA or timer and
external clock source
Clock Sources
- Internal oscillator: 24.5 MHz with ±2% accuracy
supports UART operation
- External oscillator: Crystal, RC, C, or clock (1 or 2
pin modes)
- Can switch between clock sources on-the-fly; Useful
in power saving modes
11-Pin QFN or 14-Pin SOIC Package
- QFN Size = 3x3 mm
ANALOG
PERIPHERALS
A 8-bit
M PGA 500 ksps
U
X
ADC
C8051F300/2 only
TEMP
+ SENSOR
- VOLTAGE COMPARATOR
DIGITAL I/O
UART
SMBus
PCA
Timer 0
Timer 1
Timer 2
PROGRAMMABLE PRECISION INTERNAL
OSCILLATOR
HIGH-SPEED CONTROLLER CORE
8/4/2 kBytes
ISP Flash
12
INTERRUPTS
8051 CPU
(25MIPS)
DEBUG
CIRCUITRY
256 B SRAM
POR WDT
Rev. 2.9 7/08
Copyright © 2008 by Silicon Laboratories
C8051F300/1/2/3/4/5







C8051F305 pdf, 数据表
C8051F300/1/2/3/4/5
10. Flash Memory
Figure 10.1. Flash Program Memory Map................................................................ 91
11. Oscillators
Figure 11.1. Oscillator Diagram................................................................................ 97
Figure 11.2. 32.768 kHz External Crystal Example................................................ 101
12. Port Input/Output
Figure 12.1. Port I/O Functional Block Diagram ..................................................... 103
Figure 12.2. Port I/O Cell Block Diagram ............................................................... 103
Figure 12.3. Crossbar Priority Decoder with XBR0 = 0x00 .................................... 104
Figure 12.4. Crossbar Priority Decoder with XBR0 = 0x44 .................................... 105
13. SMBus
Figure 13.1. SMBus Block Diagram ....................................................................... 111
Figure 13.2. Typical SMBus Configuration ............................................................. 112
Figure 13.3. SMBus Transaction ............................................................................ 113
Figure 13.4. Typical SMBus SCL Generation......................................................... 117
Figure 13.5. Typical Master Transmitter Sequence................................................ 123
Figure 13.6. Typical Master Receiver Sequence.................................................... 124
Figure 13.7. Typical Slave Receiver Sequence...................................................... 125
Figure 13.8. Typical Slave Transmitter Sequence.................................................. 126
14. UART0
Figure 14.1. UART0 Block Diagram ....................................................................... 131
Figure 14.2. UART0 Baud Rate Logic .................................................................... 132
Figure 14.3. UART Interconnect Diagram .............................................................. 133
Figure 14.4. 8-Bit UART Timing Diagram............................................................... 133
Figure 14.5. 9-Bit UART Timing Diagram............................................................... 134
Figure 14.6. UART Multi-Processor Mode Interconnect Diagram .......................... 135
15. Timers
Figure 15.1. T0 Mode 0 Block Diagram.................................................................. 144
Figure 15.2. T0 Mode 2 Block Diagram.................................................................. 145
Figure 15.3. T0 Mode 3 Block Diagram.................................................................. 146
Figure 15.4. Timer 2 16-Bit Mode Block Diagram .................................................. 151
Figure 15.5. Timer 2 8-Bit Mode Block Diagram .................................................... 152
16. Programmable Counter Array
Figure 16.1. PCA Block Diagram............................................................................ 155
Figure 16.2. PCA Counter/Timer Block Diagram.................................................... 156
Figure 16.3. PCA Interrupt Block Diagram ............................................................. 157
Figure 16.4. PCA Capture Mode Diagram.............................................................. 158
Figure 16.5. PCA Software Timer Mode Diagram .................................................. 159
Figure 16.6. PCA High Speed Output Mode Diagram............................................ 160
Figure 16.7. PCA Frequency Output Mode ............................................................ 161
Figure 16.8. PCA 8-Bit PWM Mode Diagram ......................................................... 162
Figure 16.9. PCA 16-Bit PWM Mode...................................................................... 163
Figure 16.10. PCA Module 2 with Watchdog Timer Enabled ................................. 164
17. C2 Interface
Figure 17.1. Typical C2 Pin Sharing....................................................................... 175
8 Rev. 2.9







C8051F305 equivalent, schematic
C8051F300/1/2/3/4/5
1.1. CIP-51™ Microcontroller Core
1.1.1. Fully 8051 Compatible
The C8051F300/1/2/3/4/5 family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51
is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can
be used to develop software. The CIP-51 core offers all the peripherals included with a standard 8052,
including two standard 16-bit counter/timers, one enhanced 16-bit counter/timer with external oscillator
input, a full-duplex UART with extended baud rate configuration, 256 bytes of internal RAM, 128 byte Spe-
cial Function Register (SFR) address space, and a byte-wide I/O Port.
1.1.2. Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute with a maximum system clock of 12 to 24 MHz. By contrast, the CIP-51 core exe-
cutes 70% of its instructions in one or two system clock cycles, with only four instructions taking more than
four system clock cycles.
The CIP-51 has a total of 109 instructions. The table below shows the total number of instructions that
require each execution time.
Clocks to Execute
1 2 2/3 3 3/4 4 4/5 5
Number of Instructions 26
50
5
14
7
3
1
2
8
1
With the CIP-51's maximum system clock at 25 MHz, it has a peak throughput of 25 MIPS. Figure 1.3
shows a comparison of peak throughputs for various 8-bit microcontroller cores with their maximum sys-
tem clocks.
25
20
15
10
5
Silicon Labs
CIP-51
(25 MHz clk)
Microchip
PIC17C75x
(33 MHz clk)
Philips
80C51
(33 MHz clk)
ADuC812
8051
(16 MHz clk)
Figure 1.3. Comparison of Peak MCU Execution Speeds
16 Rev. 2.9










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