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PDF ( 数据手册 , 数据表 ) G28F016SC-150

零件编号 G28F016SC-150
描述 BYTE-WIDE SmartVoltage FlashFile MEMORY FAMILY 4/ 8/ AND 16 MBIT
制造商 Intel Corporation
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G28F016SC-150 数据手册, 描述, 功能
E
PRELIMINARY
BYTE-WIDE
SmartVoltage FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004SC, 28F008SC, 28F016SC
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
2.7 V (Read-Only), 3.3 V or 5 V VCC
and 3.3 V, 5 V, or 12 V VPP
n High-Performance
4, 8 Mbit 85 ns Read Access Time
16 Mbit 95 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide SmartVoltage FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide SmartVoltage FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290600-003







G28F016SC-150 pdf, 数据表
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Sym
WE#
RY/BY#
VPP
VCC
GND
NC
Table 3. Pin Descriptions (Continued)
Type
Name and Function
INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
OUTPUT READY/BUSY#: Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, program, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase or
program is suspended, or the device is in deep power-down mode. RY/BY# is
always active.
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
For erasing array blocks, programming data, or configuring lock-bits.
SmartVoltage Flash 3.3 V, 5 V, and 12 V VPP
With VPP VPPLK, memory contents cannot be altered. Block erase, program, and
lock-bit configuration with an invalid VPP (see DC Characteristics) produce spurious
results and should not be attempted.
SUPPLY DEVICE POWER SUPPLY: Internal detection automatically configures the device
for optimized read performance. Do not float any power pins.
SmartVoltage Flash 2.7 V (Read-Only), 3.3 V, and 5 V VCC
With VCC VLKO, all write attempts to the flash memory are inhibited. Device
operations at invalid VCC voltages (see DC Characteristics) produce spurious
results and should not be attempted. Block erase, program, and lock-bit
configuration operations with VCC < 3.0 V are not supported.
SUPPLY GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internally connected; it may be driven or floated.
8 PRELIMINARY







G28F016SC-150 equivalent, schematic
BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
E
Table 4. Command Definitions(9)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req’d. Notes Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array/Reset
Read Identifier Codes
Read Status Register
1 Write X FFH
2
4 Write X 90H Read IA
ID
2 Write X 70H Read X SRD
Clear Status Register
1
Write X 50H
Block Erase
2 5 Write BA 20H Write BA D0H
Program
2 5,6 Write PA 40H Write PA PD
or
10H
Block Erase and Program
Suspend
Block Erase and Program
Resume
1 5 Write X B0H
1 5 Write X D0H
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
2 7 Write BA 60H Write BA 01H
2 7 Write X 60H Write X F1H
2 8 Write X 60H Write X D0H
NOTES:
1. Bus operations are defined in Table 3.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 7 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is VIH will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is VIH.
8. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
16 PRELIMINARY










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