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PDF ( 数据手册 , 数据表 ) GD25Q40

零件编号 GD25Q40
描述 Dual and Quad SPI Flash
制造商 GigaDevice
LOGO GigaDevice LOGO 


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GD25Q40 数据手册, 描述, 功能
Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
FEATURES
4M/2M/1M/512K-bit Serial Flash
-512/256/128/64K-byte
-256 bytes per programmable page
Standard, Dual, Quad SPI
-Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
-Dual SPI:SCLK, CS#, IO0, IO1, WP#, HOLD#
-Quad SPI:SCLK, CS#, IO0, IO1, IO2, IO3
High Speed Clock Frequency
-120MHz for fast read with 30PF load
-Dual I/O Data transfer up to 240Mbits/s
-Quad I/O Data transfer up to 480Mbits/s
Program/Erase Speed
-Page Program time:0.7ms typical
-Sector Erase time:150ms typical
-Block Erase time:0.3\0.5s typical
-Chip Erase time:3\2\1\0.5s typical
Flexible Architecture
-Sector of 4K-byte
-Block of 32/64K-byte
Low Power Consumption
-20mA maximum active current
-5uA maximum power down current
Software/Hardware Write Protection
Advanced security Features(1)
-Write protect all/portion of memory via software
-16-Bit Customer ID
-Enable/Disable protection with WP# Pin
-Security Architecture
-Top or Bottom, Sector or Block selection
Single Power Supply Voltage
Minimum 100,000 Program/Erase Cycles
-Full voltage range:2.7~3.6V
Note: 1.Please contact Gigadevice for details.
GENERAL DESCRIPTION
The GD25Q40/20/10/512 (4M-bit) SPI flash supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual/Quad output as well as Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO),
I/O2 (WP#), and I/O3 (HOLD#). SPI clock frequencies of up to 120MHz are supported allowing equivalent clock rates of
240MHz for Dual Output & Dual I/O read command, and 480MHz for Quad output & Quad I/O read command.
CONNECTION DIAGRAM
CS# 1
8
SO
WP#
27
Top View
36
VSS
45
8LEAD SOP/DIP
VCC
HOLD#
SCLK
SI
1







GD25Q40 pdf, 数据表
Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
Table1.1. GD25Q20 Protected area size
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
0XX0 0
00X01
00X10
01X01
01X10
0XX1 1
1X000
10001
10010
10011
1010X
10110
11001
11010
11011
1110X
11110
1X111
Blocks
NONE
3
2 and 3
0
0 and 1
0 to 3
NONE
3
3
3
3
3
0
0
0
0
0
0 to 3
Addresses
NONE
030000H – 03FFFFH
020000H – 03FFFFH
000000H – 00FFFFH
000000H – 01FFFFH
000000H – 03FFFFH
NONE
03F000H-03FFFFH
03E000H-03FFFFH
03C000H-03FFFFH
038000H-03FFFFH
038000H-03FFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
000000H-03FFFFH
Density
NONE
64KB
128KB
64KB
128KB
256KB
NONE
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB
256KB
Table1.2. GD25Q10 Protected area size
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
0XX0 0
00X01
01X01
0XX1X
1X000
10001
10010
10011
1010X
10110
11001
11010
11011
1110X
11110
1X111
Blocks
NONE
1
0
0 to 1
NONE
1
1
1
1
1
0
0
0
0
0
0 to 1
Addresses
NONE
010000H-01FFFFH
000000H-00FFFFH
000000H-01FFFFH
NONE
01F000H-01FFFFH
01E000H-01FFFFH
01C000H-01FFFFH
018000H-01FFFFH
018000H-01FFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
000000H-007FFFH
000000H-01FFFFH
Density
NONE
64KB
64KB
128KB
NONE
4KB
8KB
16KB
32KB
32KB
4KB
8KB
16KB
32KB
32KB
128KB
Portion
NONE
Upper 1/4
Upper 1/2
Lower 1/4
Lower 1/2
ALL
NONE
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
ALL
Portion
NONE
Upper 1/2
Lower 1/2
ALL
NONE
Top Block
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
ALL
8







GD25Q40 equivalent, schematic
Uniform Sector
Dual and Quad SPI Flash
GD25Q40/20/10/512
Read Data Bytes At Higher Speed (Fast Read) (0BH)
The Read Data Bytes at Higher Speed (Fast Read) command is for quickly reading data out. It is followed by a 3-byte
address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the memory content,
at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of SCLK. The
first byte addressed can be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure7. Read Data Bytes at Higher Speed Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI
SO
CS#
SCLK
SI
SO
Command
0B
High-Z
24-bit address
23 22 21
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
76543210
Data Out1
Data Out2
76543210765
MSB
MSB
Dual Output Fast Read (3BH)
The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit being
latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO.
The command sequence is shown in followed Figure8. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out.
Figure8. Dual Output Fast Read Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SI
SO
CS#
SCLK
SI
SO
Command
3B
High-Z
24-bit address
23 22 21
3210
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Clocks
64206420
Data Out1 Data Out2
75317531
MSB
MSB
6
7
16










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