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PDF ( 数据手册 , 数据表 ) SAM7S64

零件编号 SAM7S64
描述 ARM-based Flash MCU
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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SAM7S64 数据手册, 描述, 功能
AT91SAM
ARM-based Flash MCU
SAM7S512 SAM7S256 SAM7S128 SAM7S64
SAM7S321 SAM7S32 SAM7S161 SAM7S16
Features
Incorporates the ARM7TDMI® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICEIn-circuit Emulation, Debug Communication Channel Support
Internal High-speed Flash
– 512 Kbytes (SAM7S512) Organized in Two Contiguous Banks of 1024 Pages of 256
Bytes (Dual Plane)
– 256 Kbytes (SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 64 Kbytes (SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)
– 32 Kbytes (SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)
– 16 Kbytes (SAM7S161/16) Organized in 256 Pages of 64 Bytes (Single Plane)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash
Security Bit
– Fast Flash Programming Interface for High Volume Production
Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (SAM7S512/256)
– 32 Kbytes (SAM7S128)
– 16 Kbytes (SAM7S64)
– 8 Kbytes (SAM7S321/32)
– 4 Kbytes (SAM7S161/16)
Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
Reset Controller (RSTC)
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500
Hz) and Idle Mode
– Three Programmable External Clock Signals
Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two (SAM7S512/256/128/64/321/161) or One (SAM7S32/16) External Interrupt Source(s)
and One Fast Interrupt Source, Spurious Interrupt Protected
6175M–ATARM–26-Oct-12







SAM7S64 pdf, 数据表
Table 3-1. Signal Description List (Continued)
Signal Name
Function
Type
Active
Level
Two-Wire Interface
TWD
Two-wire Serial Data
I/O
TWCK
Two-wire Serial Clock
I/O
Analog-to-Digital Converter
AD0-AD3
Analog Inputs
Analog
AD4-AD7
Analog Inputs
Analog
ADTRG
ADC Trigger
Input
ADVREF
ADC Reference
Analog
Fast Flash Programming Interface
PGMEN0-PGMEN2 Programming Enabling
Input
PGMM0-PGMM3 Programming Mode
Input
PGMD0-PGMD15 Programming Data
I/O
PGMRDY
Programming Ready
Output
High
PGMNVALID
Data Direction
Output
Low
PGMNOE
Programming Read
Input
Low
PGMCK
Programming Clock
Input
PGMNCMD
Programming Command
Input
Low
Comments
Digital pulled-up inputs at reset
Analog Inputs
PGMD0-PGMD7 only on SAM7S32/16
Note: 1. Refer to Section 6. “I/O Lines Considerations” on page 14.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
8







SAM7S64 equivalent, schematic
7. Processor and Architecture
7.1 ARM7TDMI Processor
z RISC processor based on ARMv4T Von Neumann architecture
z Runs at up to 55 MHz, providing 0.9 MIPS/MHz
z Two instruction sets
z ARM® high-performance 32-bit instruction set
z Thumb® high code density 16-bit instruction set
z Three-stage pipeline architecture
z Instruction Fetch (F)
z Instruction Decode (D)
z Execute (E)
7.2 Debug and Test Features
z Integrated EmbeddedICE(embedded in-circuit emulator)
z Two watchpoint units
z Test access port accessible through a JTAG protocol
z Debug communication channel
z Debug Unit
z Two-pin UART
z Debug communication channel interrupt handling
z Chip ID Register
z IEEE1149.1 JTAG Boundary-scan on all digital pins
7.3 Memory Controller
z Bus Arbiter
z Handles requests from the ARM7TDMI and the Peripheral DMA Controller
z Address decoder provides selection signals for
z Three internal 1 Mbyte memory areas
z One 256 Mbyte embedded peripheral area
z Abort Status Registers
z Source, Type and all parameters of the access leading to an abort are saved
z Facilitates debug by detection of bad pointers
z Misalignment Detector
z Alignment checking of all data accesses
z Abort generation in case of misalignment
z Remap Command
z Remaps the SRAM in place of the embedded non-volatile memory
z Allows handling of dynamic exception vectors
z Embedded Flash Controller
z Embedded Flash interface, up to three programmable wait states
z Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states
z Key-protected program, erase and lock/unlock sequencer
z Single command for erasing, programming and locking operations
z Interrupt generation in case of forbidden operation
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
16










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