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零件编号 | MY9221 | ||
描述 | 12-channel (Support R / G / B x 4) Constant Current LED Driver | ||
制造商 | MY-Semi | ||
LOGO | |||
1 Page
MY-Semi
MY9221
12-Channel LED Driver With Grayscale
Adaptive Pulse Density Modulation Control
General Description
The MY9221, 12-channels (R/G/B x 4) c o n s t a n t
current APDM (Adaptive Pulse Density
M o d u l a t i o n ) LED driver, operates over a 3V ~ 5.5V
input voltage range. The device provides 1 2 open-drain
constant current sinking outputs that are rated to 1 7 V
and delivers up to 60mA of high accuracy current to
each string of LED. The current at each output is
programmable by means of three external current
setting resistors. MY9221 features a 1 0 M H z E M I
r e d u c t i o n data clock input. MY9221 also offers a
2-wire serial interface to send the grayscale data, control
command including 16/14/12/8-bit grayscale selection,
grayscale clock frequency division selection, output
polarity selection for high power LED driving, output Tr/Tf
timing selection, current output waveform selection, and
to realize the internal-latch function. MY9221 provides
adaptive pulse density modulation method to increase the visual
refresh rate up to 1000 Hz @ 16-bit grayscale and reduce the
flickers, and it also provides output current bilateral
processing for EMI reduction. Moreover MY9221 utilizes
clock duty recovery technique and pulse re-timing to help
long distance and multiple cascading applications.
MY9221 provides typical ±1% channel-to-channel
LED current accuracy. Additional features include a
±0.1% regulated output current capability and fast output
transient response. MY9221 is available in a 20-pin QFN
or 24-pin SSOP/TSSOP package and specified over the
-40°C to +85°C ambient temperature range.
Applications
❑ Indoor and Outdoor LED Video Displays
❑ Full Color Mesh Display
❑ Full Color Dot Matrix Module
❑ Architectural and Decorative Lighting
❑ LCD Display Backlighting
Typical Operating Circuits
Features
✦ 3 ~ 5.5V Operating supply voltage
✦ R/G/B x4 Output Channels
✦ 3~60mA@5V Constant current output range
✦ [email protected] Constant current output range
✦ Current setting by 3 external resistors
✦ 17V Rated output channels for long LED strings
✦ ±1%(typ.) LED Current accuracy between channels
✦ ±2%(typ.) LED Current accuracy between chips
✦ 20Mbps(max.) ~ 140 Kbps(min.) data rate for EMI
reduction data transfer[[[pppaaattteeennntttpppeeennndddiiinnnggg]]]
✦ 16 / 14 / 12 / 8 bit grayscale selection
✦ Built-in internal grayscale clock supports refresh rate
>1000Hz@16-bit grayscale, >256KHz@8-bit grayscale
✦ Internal Grayscale clock frequency selection for High
Power LED driving application (min. 33.6KHz)
✦ Grayscale clock source selection (SSOP & TSSOP
only): internal or external
✦ PWM or APDM control selection[[[pppaaattteeennntttpppeeennndddiiinnnggg]]]
✦ Clock duty recovery for cascading application
✦ Schmitt trigger input
✦ Output Current Tr / Tf programmable
✦ Output Current Bilateral Processing for EMI reduction
✦ -40°C to +85°C Ambient temperature range
Order information
Part Package Information
MY9221SA SOP24-236mil-1.0mm
2000 pcs/Reel
MY9221SS SSOP24-150mil-0.635mm 2500 pcs/Reel
MY9221QD QFN20-4mmx4mm-0.5mm 3000 pcs/Reel
TSSOP24-173mil-0.65mm
MY9221TE
(Exposed Pad)
Pin Configuration
2500 pcs/Reel
Nov. 2011 Ver. 1.0
SA / SS / TE
QD
MY-Semi Inc. 0
For pricing, delivery, and ordering information, please contact MY-Semi Inc. at +886-3-560-1668,
MY9221
MY-Semi
Switching Characteristics (VDD = 3.3V, Ta = 25C unless otherwise noted)
CHARACTERISTIC
SYMBOL
DCKI-to-DO
tpLH1
Propagation Delay
DCKI-to-DCKO
(‘L to ‘H’)
GCKI-to-GCKO
DI-to-DO @ Internal-latch
control cycle
Propagation Delay
(‘H’ to ‘L’)
DCKI-to-DO
DCKI-to-DCKO
GCKI-to-GCKO
tpLH2
tpLH3
tpLH4
tpHL1
tpHL2
tpHL3
DCKI
GCKI
Pulse Duration
Setup Time
Hold Time
DI @ Internal-latch
control cycle
DI @ Internal-latch
control cycle
DI
DI
DO/DCKO/GCKO Rise Time
DO/DCKO/GCKO Fall Time
Output Current Rise Time (fast)
Output Current Fall Time (fast)
Output Current Rise Time (slow)
Output Current Fall Time (slow)
DI Retiming @ Internal-latch control cycle
tw(DCK)
tw(GCK)
twH(DI)
twL(DI)
tsu(D)
th(D)
tr(DO)
tf(DO)
Tor_f
Tof_f
Tor_s
Tof_s
Tw_re
Internal-latch Start Time
Internal-latch Stop Time*
Tstart
Tstop
DCKI Freq.
F(DCKI)
Internal OSC Freq.
F(OSC)
GCKI Freq.
F(GCKI)
CONDITION
VIH = VDD
VIL = GND
Rrext = 2340
VL =5.0 V
RL = 150
CL = 13 pF
MIN.
50
50
70
230
10
10
90
220
200
0.07
6.7
TYP.
34
7.9
12
18
40
8.2
10.5
8.5
8.5
13.4
7.5
153
77
110
8.4
MAX. UNIT
39
19
19
59
19
19
7200
ns
130
us
ns
10 MHz
10.1 MHz
10 MHz
* Tstop (min.) for cascade application must > “200ns + N*10ns” (N is the cascade number of drivers)
12-Channel LED Driver with Grayscale APDM Control
Copyright© MY-Semi Inc. 7
MY9221
MY-Semi
Internal-latch control cycle timing diagram
The steps to trigger internal-latch function are shown below:
1. After whole given serial data are shifted into shift register, keeping DCKI at a fixed level
(no matter “high” or “low”) for more than 220us. (Tstart > 220us)
2. Send 4 DI pulses (twH(DI)>70ns, twL(DI)> 230ns, Tstop*)
3. Data is loaded into the latch register at 2nd falling edge of DI pulse
*Tstop (min.) for cascade application must > “200ns + N*10ns”
(N is the cascade number of drivers)
Pulse retiming at Internal-latch control cycle
MY9221 provides DO signal retiming function which is fixed at Tw_re = 90ns@VDD=5V
under internal-latch control cycle to prevent variation of the duty ratio caused by long
cascading
12-Channel LED Driver with Grayscale APDM Control
Copyright© MY-Semi Inc. 15
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页数 | 27 页 | ||
下载 | [ MY9221.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
MY9221 | 12-channel (Support R / G / B x 4) Constant Current LED Driver | MY-Semi |
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