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PDF ( 数据手册 , 数据表 ) 34903

零件编号 34903
描述 System Basis Chip
制造商 Freescale Semiconductor
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34903 数据手册, 描述, 功能
Freescale Semiconductor
Technical Data
Document Number: MC34903_4_5
Rev. 4.0, 10/2013
System Basis Chip with CAN
High Speed and LIN Interface
I3n34d49u90s03t3/r4/i/a5l
The 34903/4/5 is the second generation family of the System Basis
Chip (SBC). It combines several features and enhances present
module designs. The device works as an advanced power
management unit for the MCU with additional integrated circuits such
as sensors and CAN transceivers. It has a built-in enhanced high-speed
CAN interface (ISO11898-2 and -5) with local and bus failure
diagnostics, protection, and fail-safe operation modes. The SBC may
include zero or one LIN 2.1 interface with LIN output pin switches. It
includes up to four wake-up input pins that can also be configured as
output drivers for flexibility. This device is powered by SMARTMOS
technology.
SYSTEM BASIS CHIP
This device implements multiple Low-power (LP) modes, with very
low-current consumption. In addition, the device is part of a family
concept where pin compatibility adds versatility to module design.
EK Suffix (Pb-free)
98ASA10556D
32-PIN SOIC
The 34903/4/5 also implements an innovative and advanced fail-safe
state machine and concept solution.
Applications
Features
• Industrial process control
• Voltage regulator for MCU, 5.0 or 3.3 V, part number selectable, with
possibility of usage external PNP to extend current capability and
share power dissipation
• Voltage, current, and temperature protection
• Automation
• Motor control
• Robotics
• Extremely low quiescent current in LP modes
• Fully-protected embedded 5.0 V regulator for the CAN driver
• Multiple undervoltage detections to address various MCU
specifications and system operation modes (i.e. cranking)
• Auxiliary 5.0 or 3.3 V SPI configurable regulator, for additional ICs,
with overcurrent detection and undervoltage protection
• MUX output pin for device internal analog signal monitoring and
power supply monitoring
• Advanced SPI, MCU, ECU power supply, and critical pins
diagnostics and monitoring.
• Multiple wake-up sources in LP modes: CAN or LIN bus,
I/O transition, automatic timer, SPI message, and VDD overcurrent
detection.
• ISO11898-5 high-speed CAN interface compatibility for baud rates of
40 kb/s to 1.0 Mb/s
• Scalable product family of devices ranging from 0 to 1 LIN,
compatible to J2602-2 and LIN 2.1
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2013. All rights reserved.







34903 pdf, 数据表
PIN CONNECTIONS
PIN CONNECTIONS
VSUP1
VSUP2
I/O-3
LIN-T/I/O-2
SAFE
5V-CAN
CANH
CANL
GND CAN
SPLIT
V-BAUX
V-CAUX
V-AUX
MUX-OUT
I/O-0
DBG
MC34905S
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 GROUND 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VB
VE
RXD
TXD
VDD
MISO
MOSI
SCLK
CS
INT
RST
I/O-1
VSENSE
RXD-L
TXD-L
LIN
GND - LEAD FRAME
32 pin exposed package
VB
VSUP
I/O-3
LIN-T / I/O-2
SAFE
5V-CAN
CANH
CANL
GND CAN
SPLIT
MUX-OUT
I/O-0
DBG
NC
GND
NC
MC34903S
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 GROUND 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VE
RXD
TXD
VDD
MISO
MOSI
SCLK
CS
INT
RST
VSENSE
RXD-L
TXD-L
LIN
GND
NC
GND - LEAD FRAME
32 pin exposed package
VSUP1
VSUP2
I/O-3
I/O-2
SAFE
5V-CAN
CANH
CANL
GND CAN
SPLIT
V-BAUX
V-CAUX
V-AUX
MUX-OUT
I/O-0
DBG
MC34904
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 GROUND 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VB
VE
RXD
TXD
VDD
MISO
MOSI
SCLK
CS
INT
RST
I/O-1
VSENSE
NC
NC
NC
GND - LEAD FRAME
32 pin exposed package
VB
VSUP
I/O-3
I/O-2
SAFE
5V-CAN
CANH
CANL
GND CAN
SPLIT
MUX-OUT
I/O-0
DBG
NC
GND
NC
MC34903P
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 GROUND 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VE
RXD
TXD
VDD
MISO
MOSI
SCLK
CS
INT
RST
VSENSE
N/C
N/C
N/C
GND
NC
GND - LEAD FRAME
32 pin exposed package
Note: MC34905D, MC34905S, MC34904 and MC34903 are footprint compatible,
Figure 8. MC34905S, MC34904 and MC34903 Pin Connections
34903/4/5
8
Analog Integrated Circuit Device Data
Freescale Semiconductor







34903 equivalent, schematic
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 6. Static Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V VSUP 28 V, -40 °C TA 125 °C, unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
VDD VOLTAGE REGULATOR, VDD PIN
Output Voltage
VDD = 5.0 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
VDD = 3.3 V, VSUP 5.5 to 28 V, IOUT 0 to 150 mA
Drop voltage without external PNP pass transistor(13)
VDD = 5.0 V, IOUT = 100 mA
VDD = 5.0 V, IOUT = 150 mA
Drop voltage with external transistor(13)
IOUT = 200 mA (I_BALLAST + I_INTERNAL)
VOUT-5.0
VOUT-3.3
VDROP
VDROP-B
4.9
3.234
5.0
3.3
- 330
--
- 350
5.1
3.4
450
500
500
V
mV
mV
VSUP/1 to maintain VDD within VOUT-3.3 specified voltage range
VDD = 3.3 V, IOUT = 150 mA
VDD = 3.3 V, IOUT = 200 mA, external transistor implemented
VSUP1-3.3
V
4.0 -
-
4.0 -
-
External ballast versus internal current ratio (I_BALLAST = K x Internal current)
Output Current limitation, without external transistor
Temperature pre-warning (Guaranteed by design)
Thermal shutdown (Guaranteed by design)
Range of decoupling capacitor (Guaranteed by design)(14)
LP mode VDD ON, IOUT 50 mA (time limited)
VDD = 5.0 V, 5.6 V VSUP 28 V
VDD = 3.3 V, 5.6 V VSUP 28 V
K
ILIM
TPW
TSD
CEXT
VDDLP
1.5
150
-
160
4.7
4.75
3.135
2.0
350
140
-
-
5.0
3.3
2.5
550
-
-
100
5.25
3.465
mA
°C
°C
μF
V
LP mode VDD ON, dynamic output current capability (Limited duration. Ref. to LP-IOUTDC
-
-
50 mA
device description).
LP VDD ON mode:
Overcurrent Wake-up threshold.
Hysteresis
LP-ITH
mA
1.0 3.0
-
0.1 1.0
-
LP mode VDD ON,
device description)
drop
(13)
voltage,
at
IOUT
=
30
mA
(Limited
duration.
Ref.
to
LP-VDROP
-
200 400
mV
LP mode VDD ON, min VSUP operation (Below this value, a VDD, undervoltage
LP-MINVS
5.5
-
-
V
reset may occur)
VDD when VSUP < VSUP-TH1, at I_VDD 10 μA (Guaranteed by design)
VDD_OFF
-
-
0.3 V
VDD when VSUP VSUP-TH1, at I_VDD 40 mA (Guaranteed with parameter VDD_START UP
3.0
-
-
V
VSUP-TH1
Notes
13. For 3.3 V VDD devices, the drop-out voltage test condition leads to a VSUP below the min VSUP threshold (4.0 V). As a result, the dropout
voltage parameter cannot be specified.
14. The regulator is stable without an external capacitor. Usage of an external capacitor is recommended for AC performance.
34903/4/5
16
Analog Integrated Circuit Device Data
Freescale Semiconductor










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