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PDF ( 数据手册 , 数据表 ) ATmega128A

零件编号 ATmega128A
描述 8-bit Microcontroller
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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ATmega128A 数据手册, 描述, 功能
ATmega128A
8-bit Microcontroller with 128Kbytes
In-System Programmable Flash
DATASHEET
Features
z High-performance, Low-power Atmel® AVR® 8-bit Microcontroller
z Advanced RISC Architecture
̶ 133 Powerful Instructions – Most Single Clock Cycle Execution
̶ 32 × 8 General Purpose Working Registers + Peripheral Control Registers
̶ Fully Static Operation
̶ Up to 16MHz Throughput at 16MIPS
̶ On-chip 2-cycle Multiplier
z High Endurance Non-volatile Memory segments
̶ 128Kbytes of In-System Self-programmable Flash program memory
̶ 4Kbytes EEPROM
̶ 4Kbytes Internal SRAM
̶ Write/Erase cycles: 10,000 Flash/100,000 EEPROM
̶ Data retention: 20 years at 85°C/100 years at 25°C(1)
̶ Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
̶ Up to 64 Kbytes Optional External Memory Space
̶ Programming Lock for Software Security
̶ SPI Interface for In-System Programming
z JTAG (IEEE std. 1149.1 Compliant) Interface
̶ Boundary-scan Capabilities According to the JTAG Standard
̶ Extensive On-chip Debug Support
̶ Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG
Interface
z Peripheral Features
̶ Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
̶ Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode
and Capture Mode
̶ Real Time Counter with Separate Oscillator
̶ Two 8-bit PWM Channels
̶ 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
̶ Output Compare Modulator
̶ 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
̶ Byte-oriented Two-wire Serial Interface
̶ Dual Programmable Serial USARTs
̶ Master/Slave SPI Serial Interface
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014







ATmega128A pdf, 数据表
2.3.10 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 306.
Shorter pulses are not guaranteed to generate a reset.
2.3.11 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.12 XTAL2
Output from the inverting Oscillator amplifier.
2.3.13 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even
if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2.3.14 AREF
AREF is the analog reference pin for the A/D Converter.
2.3.15 PEN
PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high. By
holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has
no function during normal operation.
ATmega 128A [DATASHEET]
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
8







ATmega128A equivalent, schematic
Figure 6-4.
The Parallel Instruction Fetches and Instruction Executions
T1 T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6-5 shows the internal timing concept for the Register file. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 6-5. Single Cycle ALU Operation
T1
T2 T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
6.8 Reset and Interrupt Handling
The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate reset vector
each have a separate program vector in the program memory space. All interrupts are assigned individual
enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in
order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically
disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See
the section “Memory Programming” on page 274 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt vectors.
The complete list of vectors is shown in “Interrupts” on page 59. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The interrupt vectors can be moved to the start of the boot Flash
section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 59 for
more information. The Reset vector can also be moved to the start of the boot Flash section by programming
the BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 261.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is
executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For
these interrupts, the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt
handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the global
interrupt enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set, and will then be executed by order of priority.
ATmega 128A [DATASHEET]
Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014
16










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