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PDF ( 数据手册 , 数据表 ) V420H2-LH2

零件编号 V420H2-LH2
描述 TFT LCD Module
制造商 CHI MEI
LOGO CHI MEI LOGO 


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V420H2-LH2 数据手册, 描述, 功能
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V420H2-LH2 pdf, 数据表
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended
to store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item
Symbol
Power Supply Voltage
Logic Input Voltage
VCC
VIN
Value
Min.
Max.
-0.3 13.5
-0.3 3.6
Unit
V
V
Note
(1)
2.3.2 BACKLIGHT INVERTER UNIT
Item
Symbol
Value
Min.
Max.
Unit
Note
Lamp Voltage
VW Ё
3000
VRMS
Power Supply Voltage
VBL
0
30 V
(1)
Control Signal Level Ё -0.3
7 V (1), (3)
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
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V420H2-LH2 equivalent, schematic
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8 N.C.
9 GND
10 CH3[0]-
11 CH3[0]+
12 CH3[1]-
13 CH3[1]+
14 CH3[2]-
15 CH3[2]+
16 GND
17 CH3CLK-
18 CH3CLK+
19 GND
20 CH3[3]-
21 CH3[3]+
22 CH3[4]-
23 CH3[4]+
24 N.C.
25 N.C.
26 CH4[0]-
27 CH4[0]+
28 CH4[1]-
29 CH4[1]+
30 CH4[2]-
31 CH4[2]+
32 GND
33 CH4CLK-
34 CH4CLK+
35 GND
36 CH4[3]-
37 CH4[3]+
38 CH4[4]-
No Connection
Ground
Third pixel Negative LVDS differential data input. Pair 0
Third pixel Positive LVDS differential data input. Pair 0
Third pixel Negative LVDS differential data input. Pair 1
Third pixel Positive LVDS differential data input. Pair 1
Third pixel Negative LVDS differential data input. Pair 2
Third pixel Positive LVDS differential data input. Pair 2
Ground
Third pixel Negative LVDS differential clock input.
Third pixel Positive LVDS differential clock input.
Ground
Third pixel Negative LVDS differential data input. Pair 3
Third pixel Positive LVDS differential data input. Pair 3
Third pixel Negative LVDS differential data input. Pair 4
Third pixel Positive LVDS differential data input. Pair 4
No Connection
No Connection
Fourth pixel Negative LVDS differential data input. Pair 0
Fourth pixel Positive LVDS differential data input. Pair 0
Fourth pixel Negative LVDS differential data input. Pair 1
Fourth pixel Positive LVDS differential data input. Pair 1
Fourth pixel Negative LVDS differential data input. Pair 2
Fourth pixel Positive LVDS differential data input. Pair 2
Ground
Fourth pixel Negative LVDS differential clock input.
Fourth pixel Positive LVDS differential clock input.
Ground
Fourth pixel Negative LVDS differential data input. Pair 3
Fourth pixel Positive LVDS differential data input. Pair 3
Fourth pixel Negative LVDS differential data input. Pair 4
(1)
(1)
(1)
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