DataSheet8.cn


PDF ( 数据手册 , 数据表 ) Z8030

零件编号 Z8030
描述 Communications Controller
制造商 Zilog
LOGO Zilog LOGO 


1 Page

No Preview Available !

Z8030 数据手册, 描述, 功能
Zilog
Z8030 Z8000®
Z-SCC Serial
Communications Controller
Product
Specification
Features
General
Description
• Two independent, 0 to 1.5M bit/second, full-
duplex channels, each with a separate crystal
OSCillator, baud rate generator, and Digital
Phase-Locked Loop for clock recovery.
• Multi-protocol operation under program
control; programmable for NRZ, NRZI, or
FM data encoding.
• Asynchronous mode with five to eight bits
and one, one and one-half, or two stop bits
per character; programmable clock factor;
break detection and generation; parity,
overrun, and framing error detection.
• Synchronous mode with internal or external
character synchronization on one or two
The Z8030 Z-SCC Serial Communications
Controller is a dual-channel, multi-protocol
data communications peripheral designed for
use with the Zilog Z-Bus. The Z-SCC functions
as a serial-to-parallel, parallel-to-serial con-
verter/controller. The Z-SCC can be software-
configured to satisfy a wide variety of serial
April 1985
synchronous characters and CRC genera-
tion and checking with CRC-16 or
CRC-CCITT preset to either Is or Os.
• SDLC/HDLC mode with comprehensive
frame-level control, automatic zero insertion
and deletion, I-field residue handling, abort
generation and detection, CRC generation
and checking, and SDLC Loop mode
operation.
• Local Loopback and Auto Echo modes.
• 1.544M bit/second Tl digital trunk compatible
version available.
communications applications. The device con-
tains a variety of new, sophisticated internal
functions including on-chip baud rate
generators, Digital Phase-Locked Loops, and
crystal oscillators that dramatically reduce the
need for external logic.
2016-001,002
ADDRESS'
DATA BUS
AD,
TxDA
} SERIAL
AD, RIlOA _ _ DATA
AD, TRxCA ........-} CHANNEL
AD, RTxCA .--- CLOCKS
AD,
AD, CHANNEL
AD, CONTROLS
FOR MODEM,
ADo DMA,OR
As OTHER
OS
R/W
es,
} SERIAL
_ _ DATA
esc
INT
INTACK
lEI
lEO
-\IRTxes
._...._...
I\
CHANNEL
CLOCKS
SYNCe
WIREOB
DTR/REQB
RlSB
CHANNEL
CONTROLS
FDOMRAM,OORDEM,
Z8030 else __ OTHER
z·scc DeDS
CH·A
CH·B
ttt
+5V GND PCLK
Figure I. Pin Funcllons
AD,
AD,
AD,
AD,
iNT
lEO
lEi
INTACK
+sv
WIREQA
SYNCA
RheA
RIlOA
TRxCA
hDA
OTR/REQA
RlSA
elSA
DeCA
PClK
ADO
39 AD,
38 AD,
37 AD,
36 OS
35 As
34 RIW
Z8030
z·scc
11
33
32
31
30
eso
es,
GND
W/REoe
12 29 SYNCe
"13 RTxCB
37 RKOB
26 TRlleB
16 25 1)(D8
24 DTRIREQB
18 23 Rlse
19 22 elSS
21 DC De
Figure 2. 40-pin Dual-In-Line Package (DIP).
Pin Assignments
631







Z8030 pdf, 数据表
Functional
Description
(Continued)
read; depending on its contents, the CPU
either writes data, reads data, or continues.
Two bits in the register indicate the need for
data transfer. An alternative is a poll of the
Interrupt Pending register to determine the
source of an interrupt. The status for both
channels resides in one register.
Interrupts. The Z-SCC interrupt scheme con-
forms to the Z-Bus specification. When a
Z-SCC responds to an Interrupt Acknowledge
signal (INTACK) from the CPU, an interrupt
vector may be placed on the AID bus. This
vector is written in WR2 and may be read in
RR2A or RR2B (Figures 10 and II).
To speed interrupt response time, the Z-SCC
can modify three bits in this vector to indicate
status. If the vector is read in Channel A,
status is never included; if it is read in
Channel B, status is always included.
Each of the six sources of interrupts in the
Z-SCC (Transmit, Receive, and External/Status
interrupts in both channels) has three bits
associated with the interrupt source: Interrupt
Pending (IP), Interrupt Under Service (IUS),
and Interrupt Enable (IE). Operation of the IE
bit is straightforward. If the IE bit is set for a
given interrupt source, then that source can
request interrupts. The exception is when the
MIE (Master Interrupt Enable) bit in WR9 is
reset and no interrupts may be requested. The
IE bits are write only.
The other two bits are related to the Z-Bus
interrupt priority chain (Figure 7). As a Z-Bus
peripheral, the Z-SCC may request an
interrupt only when no higher priority device
is requesting one, e.g., when lEI is High. If
the device in question requests an interrupt, it
pulls down INT. The CPU then responds with
INTACK, and the interrupting device places
the vector on the AID bus.
In the Z-SCC, the IP bit signals a need for
interrupt servicing. When an IP bit is I and
the IEI input is High, the INT output is pulled
Low, requesting an interrupt. In the Z-SCC, if
the IE bit is not set by enabling interrupts,
then the IP for that souree can never be set.
The IP is set two or three AS cycles after the
interrupt condition occurs. Two or three AS
rising edges are required from the time an in-
terrupt condition occurs until INT is activated.
The IP bits are readable in RR3A.
The IUS bits signal that an interrupt request
is being serviced. If an IUS is set, all interrupt
sources of lower priority in the Z-SCC and
external to the Z-SCC are prevented from
requesting interrupts. The internal interrupt
sources are inhibited by the state of the inter-
nal daisy chain, while lower priority devices
are inhibited by the IEO output of the Z-SCC
being pulled Low and propagated to subse-
quent peripherals. An IUS bit is set during an
Interrupt Acknowledge cycle if there are no
higher priority devices requesting interrupts.
There are three types of interrupts:
Transmit, Receive, and External/Status. Each
interrupt type is enabled under program con-
trol with Channel A having higher priority
than Channel B, and with Receiver, Transmit,
and External/Status interrupts prioritized in
that order within each channel. When the
Transmit interrupt is enabled, the CPU is
interrupted when the transmit buffer becomes
empty. (This implies that the transmitter must
have had a data character written into it so
that it can become empty.) When enabled, the
receiver can interrupt the CPU in one of
three ways:
• Interrupt on First Receive Character or
Special Receive Condition.
• Interrupt on All Receive Characters or
Special Receive Condition.
• Interrupt on Special Receive Condition
Only.
Interrupt on First Character or Special Con-
dition and Interrupt on Special Condition Only
are typically used with the Block Transfer
mode. A Special Receive Condition is one of
the following: receiver overrun, framing error
in Asynchronous mode, end-of-frame in SDLC
mode and, optionally, a parity error. The
Special Receive Condition interrupt is different
from an ordinary receive charader available
interrupt only in the status placed in the vector
during the Interrupt Acknowledge cycle. In
Interrupt on First Receive Character, an inter-
rupt can occur from Special Receive Condi-
tions any time after the first receive character
interrupt.
The main function of the External/Status
interrupt is to monitor the signal transitions of
the CTS, DCD, and SYNC pins; however, an
External/Status interrupt is also caused by a
Transmit Underrun condition, or a zero count
+5V
Z·BUS
PERIPHERAL
lEI ADo-AD1 INT INTACK lEO
Z·BUS
PERIPHERAL
lEI ADo-AD7 'NT INTACK lEO
Z·BUS
PERIPHERAL
tEl ADo-AD7 ,NT i"NTACK
638
ADO-AD7 \ r - - - - - - - - - - - - - - - - - - - - - - - - - - '
'NT _ - - - - - -.....- I - - - - - - - -.....- + - - - - - - - - - ' - - t - - - J
'NTACK ......- - - - - - - - ' - - - - - - - - - - - " - - - - - - - - - - - '
Figure 7. Z-BUS Interrupt Schedule
2016·008







Z8030 equivalent, schematic
Timing
(Continued)
cycle. Between the rising edge of AS and the
falling edge of DS, the internal and external
lEI/lEO daisy chains settle. If there is an inter-
rupt pending in the Z-SCC and lEI is High
when DS falls, the Acknowledge cycle was
intended for the Z-SCC. In this case, the
Z-SCC may be programmed to respond to DS
Low by placing its interrupt vector on
ADO-AD? It then sets the appropriate
Interrupt-Under-Service latch internally.
ADO-AD7 ~=(~IG~N~O~RE~D:)=)~----f."''''----C=X,-_V_E_CT_O_R_-J}-
;'
Absolute
Maximum
Ratings
Standard
Test
Conditions
Figure 14. Interrupt Acknowledge Cycle Timing
Voltages on all inputs and outputs
with respect to GND
-0.3 V to + 7.0 V
Operating Ambient
Temperature
As Specified in
Ordering Information
Storage Temperature
-65°C to + 150°C
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the device.
This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections
of these specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The characteristics below apply for the
folloWing standard test conditions, unless
otherwise noted. All voltages are referenced to
GND. Positive current flows into the refer-
enced pin. Standard conditions are as follows:
+5V
2.1K
• +4.75 V,.;; Vee";; +5.25 V
• GND = 0 V
• TA as speCified in Ordering Information
All ac parameters assume a load capacitance
of 50 pF max.
.5V
irFROM OUTPUT
UNDER TEST
2.2K
SO pI
Figure 15. Standard Te.t Load
Figure 16. Open-Drain Te.t Load
DC
Charac-
teristics
Symbol
Parameter
Min Max
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Vee Supply Current
2.0
-0.3
2.4
Vee+ 0.3
0.8
0.4
± 10.0
± 10.0
250
Vee == 5 V ± 5% unless otherwise specified, over specified temperature range.
Unit
V
V
V
V
I'A
pA.
rnA
Condition
IoH = - 25O I'A
IOL = +2.0 rnA
0.4 ,;; VIN ,;; +2.4V
0.4 ,;; Your ,;; +2.4V
Capacitance Symbol
Parameter
Min
CrN
Cour
CliO
Input Capacitance
Output Capacitance
Bidirectional Capacitance
f = 1 MHz, over speCified temperature range.
646
Max Unit
10 pi
15 pi
20 pi
Test Condition
Unmeasured Pins
Returned to Ground
2016~O14 8085~006, 001










页数 22 页
下载[ Z8030.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
Z8030Communications ControllerZilog
Zilog
Z8036Z-CIO AND CIO COUNTER/TIMER AND PARALLEL I/O UNITZilog.
Zilog.
Z8038Z-FIO / FIFO Input / Output Interface UnitST Microelectronics
ST Microelectronics
Z80380MicroprocessorZilog
Zilog

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap