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PDF ( 数据手册 , 数据表 ) M200O3-L01

零件编号 M200O3-L01
描述 TFT LCD Module
制造商 Chi Mei
LOGO Chi Mei LOGO 


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M200O3-L01 数据手册, 描述, 功能
Global LCD Panel Exchange Center
www.panelook.com
Doc No.: 400043794
Issued Date :04,Feb,2010
Model No.: M200O3-L01
Approval
TFT LCD Approval Specification
MODEL NO.: M200O3- L01
Customer:
Approved by:
Note:
TPV
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2010-02-10
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2010.02.10
Director Accept
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M200O3-L01 pdf, 数据表
Global LCD Panel Exchange Center
www.panelook.com
Doc No.: 400043794
Issued Date :04,Feb,2010
Model No.: M200O3-L01
Approval
Note (3) The specified power supply current is under the conditions at Vcc = 5.0 V, Ta = 25 ± 2 ºC, fv = 60
Hz, whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
Active Area
c. Vertical Stripe Pattern
Active Area
RGB RGB
BRGB RGBR
BRGB RGBR
RGB RGB
Active Area
Note (4) The power consumption is specified at the pattern with the maximum current
Note (5) VID waveform condition
Note (6) The Rush current would be happened when system doesn’t follow Power sequence in AC off status.
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M200O3-L01 equivalent, schematic
Global LCD Panel Exchange Center
www.panelook.com
Doc No.: 400043794
Issued Date :04,Feb,2010
Model No.: M200O3-L01
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Clock
LVDS Data
Vertical Active Display Term
Horizontal Active Display Term
Item
Symbol
Frequency
Fc
Period
Tc
Input cycle to
cycle jitter
Trcl
Spread
spectrum
modulation Fclkin_mod
range
Spread
spectrum
modulation
FSSM
frequency
High Time
Tch
Low Time
Tcl
Setup Time Tlvs
Hold Time
Tlvh
Frame Rate Fr
Total
Tv
Display
Tvd
Blank
Tvb
Total
Th
Display
Thd
Blank
Thb
Min.
48.3
-
-
-2%Fc
-
-
-
600
600
50
929
900
Tv-Tvd
1040
800
Th-Thd
Typ.
59.2
16.89
-
-
-
4/7
3/7
-
-
60
934
900
Tv-Tvd
1056
800
Th-Thd
Max.
75.7
-
+2%Tc
+2%Fc
200
-
-
-
-
75
942
900
Tv-Tvd
1072
800
Th-Thd
Unit
MHz
ns
ps
Note
-
(1)
MHz
KHz
(2)
Tc -
Tc -
ps
ps
(3)
Hz Tv=Tvd+Tvb
Th -
Th -
Th -
Tc Th=Thd+Thb
Tc -
Tc -
Note: Because this module is operated by DE only mode, Hsync and Vsync input signals are ignored.
DE
DCLK
DE
DATA
INPUT SIGNAL TIMING DIAGRAM
Tv
TVd
TVb
TC Thb
Th
Thd
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