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PDF ( 数据手册 , 数据表 ) M190A1-L0C

零件编号 M190A1-L0C
描述 LCD MODULE
制造商 CHI MEI
LOGO CHI MEI LOGO 


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M190A1-L0C 数据手册, 描述, 功能
Global LCD Panel Exchange Center
www.panelook.com
Doc. No.: 44086418
Issued Date: Jul, 04, 2008
Model No.: M190A1-L0C
Approval
TFT LCD Approval Specification
MODEL NO.: M190A1-L0C
Customer:
Approved by:
Note:
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2008-10-14
10:44:48 CST
PMMD II
Director
kevin_wu(ܦਹᕬ
/56520/54894)
Director Accept
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M190A1-L0C pdf, 数据表
Global LCD Panel Exchange Center
www.panelook.com
Doc. No.: 44086418
Issued Date: Jul, 04, 2008
Model No.: M190A1-L0C
Approval
Note (3) The specified power supply current is under the conditions at Vcc = 5.0 V, Ta = 25 ± 2 ºC, fv = 60
Hz, whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
Active Area
c. Vertical Stripe Pattern
Active Area
3.2 Vcc POWER DIP CONDITION:
Active Area
RGB RGB
BRGB RGBR
BRGB RGBR
RGB RGB
4.0V
Vcc
4.5V
Td
Dip condition: 4.0V d Vcc d 4.5V ,Td d 20ms
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M190A1-L0C equivalent, schematic
Global LCD Panel Exchange Center
www.panelook.com
Doc. No.: 44086418
Issued Date: Jul, 04, 2008
Model No.: M190A1-L0C
Approval
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the
diagram below.
- Power Supply
for LCD, Vcc
0V
- Interface Signal
(LVDS Signal of
Transmitter), VI
0V
- Power for Lamp
Power On
90%
10%
t1
t2
Power Off Restart
90%
10%
t4
t3
Valid Data
t5 t6
50%
50%
OFF ON OFF
10%
Timing Specifications:
0.5< t1 Љ 10 msec
0 < t2 Љ 50 msec
0 < t3 Љ 50 msec
t4 Њ 500 msec
t5 Њ 450 msec
t6 Њ 90 msec
Note.
(1) The supply voltage of the external system for the module input should be the same as the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation of the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of Vcc = off level, please keep the level of input signals on the low or keep a high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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