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零件编号 | V400H1-P02 | ||
描述 | TFT LCD Module | ||
制造商 | CMI MEI | ||
LOGO | |||
1 Page
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
TFT LCD Approval Specification
MODEL NO.: V400H1 - P02
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Customer:
Approved by:
Note:
Approved By
TVHD
CC Chung
Reviewed By
QA Dept.
Hsin-nan Chen
Product Development Div.
WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Josh Chi
Karen Liao
1
Version 2.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
GND
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
470us
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60 Hz,
whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
Active Area
c. Horizontal Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
8
Version 2.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Nov. 19, 2009
Model No.: V400H1 - P02
Approval
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
Item
Symbol Min.
Typ.
Max.
Unit
Note
LVDS
Receiver
Clock
LVDS
Receiver
Data
Vertical
Active
Display
Term
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time
Fclkin
(=1/TC)
Trcl
Fclkin_mod
FSSM
Tlvsu
60
-
Fclkin-2%
-
600
74.25
-
-
-
-
Hold Time
Tlvhd
600
-
Frame Rate
Total
Display
Blank
Fr5 57 60
Fr6 47 50
Tv 1115 1125
Tvd 1080 1080
Tvb 35 45
80
200
Fclkin+2%
200
-
-
63
53
1135
1080
55
MHz
ps
MHz
KHz
ps
ps
Hz
Hz
Th
Th
Th
(3)
(4)
(5)
(6)
Tv=Tvd+Tvb
Ё
Ё
Horizontal
Active
Display
Term
Total
Display
Blank
Th 1050 1100
Thd 960 960
Thb 90 140
1150
960
190
Note (1) Please make sure the range of pixel clock has follow the below equationΚ
Tc
Tc
Tc
Th=Thd+Thb
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Ё
Fclkin(max) Њ Fr6 Ѽ Tv Ѽ Th
Fr5 Ѽ Tv Ѽ Th Њ Fclkin(min)
Note (2) This module is operated in DE only mode and please follow the input signal timing diagram belowΚ
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16
Version 2.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com
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页数 | 28 页 | ||
下载 | [ V400H1-P02.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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