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PDF ( 数据手册 , 数据表 ) V400H1-L10

零件编号 V400H1-L10
描述 TFT LCD Module
制造商 CMI MEI
LOGO CMI MEI LOGO 


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V400H1-L10 数据手册, 描述, 功能
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Jan. 15, 2010
Model No.: V400H1 - L10
Under Evaluation
TFT LCD Evaluation Specification
MODEL NO.: V400H1 - L10
Approved By
TVHD
CC Chung
Reviewed By
QA Dept.
Hsin-nan Chen
Product Development Div.
WT Lin
LCD TV Marketing and Product Management Div.
Prepared By
Josh Chi
Karen Liao
1
The information described in this technical specification is tentative and it is possible to be changed without prior notice.
Please contact CMO ’s representative while your product design is based on this specification.
Version 1.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com







V400H1-L10 pdf, 数据表
Global LCD Panel Exchange Center
www.panelook.com
GND
Vcc rising time is 470us
+12V
0.9Vcc
0.1Vcc
470us
Issued Date: Jan. 15, 2010
Model No.: V400H1 - L10
Under Evaluation
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 60
Hz, whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
Active Area
c. Horizontal Pattern
Active Area
8
The information described in this technical specification is tentative and it is possible to be changed without prior notice.
Please contact CMO ’s representative while your product design is based on this specification.
Version 1.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com







V400H1-L10 equivalent, schematic
Global LCD Panel Exchange Center
www.panelook.com
Issued Date: Jan. 15, 2010
Model No.: V400H1 - L10
Under Evaluation
34 GND
Ground
35 ERX3-
36 ERX3+
Even pixel Negative LVDS differential data input. Channel 3
Even pixel Positive LVDS differential data input. Channel 3
(1)
37 N.C.
38 N.C.
No Connection
No Connection
(3)
39 GND
Ground
40 N.C.
No Connection
41 N.C.
No Connection
42 N.C.
No Connection
(3)
43 N.C.
No Connection
44 N.C.
No Connection
45 LVDS_SEL High(3.3V) or open for VESA, Low (GND) for JEIDA
(4)
46 N.C.
No Connection
47 N.C.
No Connection
48 N.C.
49 N.C.
No Connection
No Connection
(3)
50 N.C.
No Connection
51 N.C.
No Connection
Note (1) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel
Note (2) LVDS connector pin order defined as follows
Note (3) Reserved for internal use. Please leave it open.
Note (4) Low: JEIDA LVDS Format (Connect to GND), High or open: VESA Format. (Connect to +3.3V)
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
16
The information described in this technical specification is tentative and it is possible to be changed without prior notice.
Please contact CMO ’s representative while your product design is based on this specification.
Version 1.0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory! www.panelook.com










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