DataSheet8.cn


PDF ( 数据手册 , 数据表 ) ADE7913

零件编号 ADE7913
描述 Sigma-Delta ADC
制造商 Analog Devices
LOGO Analog Devices LOGO 


1 Page

No Preview Available !

ADE7913 数据手册, 描述, 功能
Data Sheet
FEATURES
Two (ADE7912) or three (ADE7913) 24-bit isolated, Σ-Δ
analog-to-digital converters (simultaneously sampling
ADCs)
Integrated isoPower, isolated dc-to-dc converter
On-chip temperature sensor
4-wire SPI serial interface
Up to 4 ADE7912/ADE7913 devices clocked from a single
crystal or an external clock
Synchronization of multiple ADE7912/ADE7913 devices
±31.25 mV peak input range for current channel
±500 mV peak input range for voltage channels
Reference drift: 10 ppm/°C typical
Single 3.3 V supply
20-lead, wide-body SOIC package with 8.3 mm creepage
Operating temperature: −40°C to +85°C
Safety and regulatory approvals (pending)
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice #5A
IEC 61010-1: 400 V rms
VDE certificate of conformity
DIN VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 846 V peak
APPLICATIONS
Shunt-based polyphase meters
Power quality monitoring
Solar inverters
Process monitoring
Protective devices
Isolated sensor interfaces
Industrial PLCs
GENERAL DESCRIPTION
The ADE7912/ADE79131 are isolated, 3-channel Σ-Δ ADCs for
polyphase energy metering applications using shunt current
sensors. Data and power isolation are based on the Analog Devices,
Inc., iCoupler® technology. The ADE7912 features two 24-bit
ADCs, and the ADE7913 features three ADCs. The current ADC
provides a 67 dB signal-to-noise ratio over a 3 kHz signal
bandwidth, whereas the voltage ADCs provide a SNR of 72 dB over
the same bandwidth. One channel is dedicated to measuring the
3-Channel, Isolated,
Sigma-Delta ADC with SPI
ADE7912/ADE7913
TYPICAL APPLICATIONS CIRCUIT
PHASE PHASE PHASE
NEUTRAL
A
B
C
ISOLATION
BARRIER
LOAD
EARTH
V1P
VM
IM PHASE A
ADE7912/
IP ADE7913
V2P
3.3V
GNDISO_A
GNDMCU
V1P
VM
IM PHASE B
ADE7912/
IP ADE7913
V2P
3.3V
GNDISO_B
GNDMCU
V1P
VM
IM PHASE C
ADE7912/
IP ADE7913
V2P
3.3V
GNDISO_C
GNDMCU
V1P
VM NEUTRAL
IM
LINE
ADE7912/
ADE7913
IP (OPTIONAL)
V2P
3.3V
GNDISO_N
GNDMCU
Figure 1.
3.3V
GNDMCU
voltage across a shunt when the shunt is used for current sensing.
Up to two additional channels are dedicated to measuring
voltages, which are usually sensed using resistor dividers. One
voltage channel can be used to measure the temperature of the die
via an internal sensor. The ADE7913 includes three channels:
one current and two voltage channels. The ADE7912 has one
voltage channel but is otherwise identical to the ADE7913.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; 7,558,080. Other patents are pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







ADE7913 pdf, 数据表
ADE7912/ADE7913
Data Sheet
3.0
2.5
2.0
1.5
1.0
0.5
0
0 50 100 150 200
AMBIENT TEMPERATURE (ºC)
Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10
TIMING CHARACTERISTICS
VDD = 3.3 V ± 10%, GND = 0 V, on-chip reference, CLKIN = 4.096 MHz, TMIN to TMAX = −40°C to +85°C.
Table 5. SPI Interface Timing Parameters
Parameter
CS to SCLK Positive Edge
SCLK Frequency1
SCLK Low Pulse Width
SCLK High Pulse Width
Data Output Valid After SCLK Edge
Data Input Setup Time Before SCLK Edge
Data Input Hold Time After SCLK Edge
Data Output Fall Time
Data Output Rise Time
SCLK Rise Time
SCLK Fall Time
MISO Disable After CS Rising Edge
CS High After SCLK Edge
Symbol
tSS
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDIS
tSFS
Min Max
50
250 5600
80
80
80
70
20
20
20
20
20
5 40
0
1 Minimum and maximum specifications are guaranteed by design.
Unit
ns
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 8 of 44







ADE7913 equivalent, schematic
ADE7912/ADE7913
TERMINOLOGY
Pseudo Differential Signal Voltage Range Between IP and
IM, V1P and VM, and V2P and VM Pins
The range represents the peak-to-peak pseudo differential
voltage that must be applied to the ADCs to generate a full-scale
response when the IM and VM pins are connected to GNDISO,
Pin 2. The IM and VM pins are connected to GNDISO using
antialiasing filters (see Figure 20). Figure 21 illustrates the input
voltage range between IP and IM; Figure 22 illustrates the input
voltage range between V1P and VM and between V2P and VM.
+31.25mV
IP
0V
IM 0V
IP – IM
–31.25mV
+31.25mV
0V
–31.25mV
Figure 21. Pseudo Differential Input Voltage Range Between IP and IM Pins
V1P, V2P
+500mV
0V
VM 0V
V1P – VM,
V2P – VM
0V
–500mV
+500mV
–500mV
Figure 22. Pseudo Differential Input Voltage Range Between V1P and VM
Pins and Between V2P and VM
Maximum VM and IM Voltage Range
The range represents the maximum allowed voltage at VM and
IM pins relative to GNDISO, Pin 10.
Data Sheet
Crosstalk
Crosstalk represents leakage of signals, usually via capacitance
between circuits. Crosstalk is measured in the current channel
by setting the IP and IM pins to GNDISO, Pin 10, supplying a
full-scale alternate differential voltage between the V1P and VM
pins and between the V2P and VM pins of the voltage channel,
and measuring the output of the current channel. It is measured
in the V1P voltage channel by setting the V1P and VM pins to
GNDISO, Pin 10, supplying a full-scale alternate differential voltage
at the IP and V2P pin, and measuring the output of the V1P
channel. Crosstalk is measured in the V2P voltage channel by
setting the V2P and VM pins to GNDISO, Pin 10, supplying a full-
scale alternate differential voltage at the IP and V1P pins, and
measuring the output of the V2P channel. The crosstalk is equal
to the ratio between the grounded ADC output value and its
ADC full-scale output value. The ADC outputs are acquired for
2 sec. Crosstalk is expressed in decibels.
Input Impedance to Ground (DC)
The input impedance to ground represents the impedance
measured at each ADC input pin (IP, IM, V1P, V2P, and VM)
with respect to GNDISO, Pin 10.
Differential Input Impedance (DC)
The differential input impedance represents the impedance
measured between the ADC inputs: IP and IM, V1P and VM,
and V2P and VM (ADE7913 only).
ADC Offset Error
ADC offset error is the difference between the average
measured ADC output code with both inputs connected to
GNDISO and the ideal ADC output code. The magnitude of
the offset depends on the input range of each channel.
ADC Offset Drift over Temperature
The ADC offset drift is the change in offset over temperature.
It is measured at −40°C, +25°C, and +85°C. The offset drift over
temperature is computed as follows:
Drift =
Offset(40) Offset(25) Offset(85) Offset(25)
max

Offset(25)× (40 25)
,
Offset(25)× (85 25)

Offset drift is expressed in nV/°C.
Gain Error
The gain error in the ADCs represents the difference between the
measured ADC output code (minus the offset) and the ideal
output code when the internal voltage reference is used (see
the Analog-to-Digital Conversion section). The difference is
expressed as a percentage of the ideal code. It represents the
overall gain error of one current or voltage channel.
Rev. 0 | Page 16 of 44










页数 30 页
下载[ ADE7913.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
ADE7912Sigma-Delta ADCAnalog Devices
Analog Devices
ADE7913Sigma-Delta ADCAnalog Devices
Analog Devices

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap