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PDF ( 数据手册 , 数据表 ) M200FGJ-L2U

零件编号 M200FGJ-L2U
描述 TFT LCD Module
制造商 CHIMEI Innolux
LOGO CHIMEI Innolux LOGO 


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M200FGJ-L2U 数据手册, 描述, 功能
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
Doc. Number :
ɝ Tentative Specification
ϭ Preliminary Specification
ϭ Approval Specification
MODEL NO.: M200FGJ
SUFFIX: L2U
Customer:
APPROVED BY
SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your
signature and comments.
Approved By Checked By Prepared By
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copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
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M200FGJ-L2U pdf, 数据表
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
4.2. INTERFACE CONNECTIONS
PIN ASSIGNMENT
Pin Name
1 RXO0-
2 RXO0+
3 RXO1-
4 RXO1+
5 RXO2-
6 RXO2+
7 GND
8 RXOC-
9 RXOC+
10 RXO3-
11 RXO3+
12 RXE0-
13 RXE0+
14 GND
15 RXE1-
16 RXE1+
17 GND
18 RXE2-
19 RXE2+
20 RXEC-
21 RXEC+
22 RXE3-
23 RXE3+
24 GND
25 NC
26 NC
27 NC
28 Vcc
29 Vcc
30 Vcc
Description
Negative LVDS differential data input. Channel O0 (odd)
Positive LVDS differential data input. Channel O0 (odd)
Negative LVDS differential data input. Channel O1 (odd)
Positive LVDS differential data input. Channel O1 (odd)
Negative LVDS differential data input. Channel O2 (odd)
Positive LVDS differential data input. Channel O2 (odd)
Ground
Negative LVDS differential clock input. (odd)
Positive LVDS differential clock input. (odd)
Negative LVDS differential data input. Channel O3(odd)
Positive LVDS differential data input. Channel O3 (odd)
Negative LVDS differential data input. Channel E0 (even)
Positive LVDS differential data input. Channel E0 (even)
Ground
Negative LVDS differential data input. Channel E1 (even)
Positive LVDS differential data input. Channel E1 (even)
Ground
Negative LVDS differential data input. Channel E2 (even)
Positive LVDS differential data input. Channel E2 (even)
Negative LVDS differential clock input. (even)
Positive LVDS differential clock input. (even)
Negative LVDS differential data input. Channel E3 (even)
Positive LVDS differential data input. Channel E3 (even)
Ground
For LCD internal use only, Do not connect
For LCD internal use only, Do not connect
For LCD internal use only, Do not connect
+5.0V power supply
+5.0V power supply
+5.0V power supply
Note (1) Connector Part No.:
GS23302-0011R-7F (Foxconn) or 187106-30091(P-TWO) or equivalent
Note (2) User’s connector Part No:
Mating Wire Cable Connector Part No.: FI-X30H(JAE) or FI-X30HL(JAE)
Mating FFC Cable Connector Part No.: 217007-013001 (P-TWO) or JF05X030-1 (JAE).
Note (3) The first pixel is odd.
Note (4) Input signal of even and odd clock should be the same timing.
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copyright belongs to CHIMEI InnoLux. Any unauthorized use is prohibited.
The
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M200FGJ-L2U equivalent, schematic
Global LCD Panel Exchange Center
www.panelook.com
PRODUCT SPECIFICATION
4.5 DISPLAY TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal
LVDS Clock
Vertical Display Term
Horizontal Display Term
Item Symbol Min.
Frequency Fc
Period
Tc
Input cycle to
cycle jitter
Trcl
-0.02*TC
Input Clock
to data skew
TLVCCS
-0.02*TC
Spread
spectrum
modulation
Fclkin_
mod
0.97*FC
range
Spread
spectrum
modulation
FSSM
-
frequency
Frame Rate Fr
-
Total Tv -
Active
Display
Tvd
-
Blank
Tvb
-
Total Th -
Active
Display
Thd
-
Blank
Thb
-
Typ.
48.5
13.1
-
-
-
-
50
905
900
5
950
800
150
Max.
0.02*TC
0.02*TC
1.03*FC
100
-
-
-
-
-
-
-
Unit
MHz
ns
ns
Note
-
(1)
(2)
MHz
KHz
(3)
Hz Tv=Tvd+Tvb
Th -
Th -
Th -
Tc Th=Thd+Thb
Tc -
Tc -
Note: Because this module is operated by DE only mode, Hsync and Vsync input signals are ignored.
INPUT SIGNAL TIMING DIAGRAM
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