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零件编号 | T420HW06-V4 | ||
描述 | TFT LCD Module | ||
制造商 | AUO | ||
LOGO | |||
1 Page
T420HW06 V4 Product Specification
Rev.0 0
Model Name: T420HW06 V4
Issue Date : 2010/11/19
(*)Preliminary Specifications
( )Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
Yen Ting Chiu
____________________________________
Note
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Angus Liu
____________________________________
Prepared By PM
Cynthia Hung
____________________________________
© Copyright AUO Optronics Corp. 2009 All Rights Reserved.
Page 1 / 32
T420HW06 V4 Product Specification
Rev.0 0
4. The measure points of V IH and VIL are in LCM side after connecting the System Board and LCM.
5. Input Channel Pair Skew Margin
Note: x = 0, 1, 2, 3, 4
6. LVDS Receiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
Fclk_ss(max)
1/FSS
Fclk
Fclk_ss(min)
7. Receiver Data Input Margin
Parameter
Symbol
Input Clock Frequency
Input Data Position0
Input Data Position1
Input Data Position2
Input Data Position3
Input Data Position4
Input Data Position5
Input Data Position6
Fclk
tRIP1
tRIP0
tRIP6
tRIP5
tRIP4
tRIP3
tRIP2
Min
Fclk (min)
-|tRMG|
T/7-|tRMG|
2T/7-|tRMG|
3T/7-|tRMG|
4T/7-|tRMG|
5T/7-|tRMG|
6T/7-|tRMG|
Rating
Type
--
0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
Max
Fclk (max)
|tRMG|
T/7+|tRMG|
2T/7+|tRMG|
3T/7+|tRMG|
4T/7+|tRMG|
5T/7+|tRMG|
6T/7+|tRMG|
Unit Note
MHz
ns
ns
ns
ns
ns
ns
ns
T=1/Fclk
© Copyright AUO Optronics Corp. 2009 All Rights Reserved.
Page 8 / 32
Power Sequence for LCD
Power Supply For LCD
VDD (+12V)
GND
90%
10%
t1
Interface Signal
(LVDS Data & CLK)
GND
t2
Backlight on/off
control signal
(VBLON)
GND
CMOS Interface Signal
GND
t8
T420HW06 V4 Product Specification
Rev.0 0
Valid Data
90%
10%
10%
t5 t6
t7
t3 t4
t9
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
Values
Min. Type. Max.
0.4 --- 30
0.1 --- 50
450 ---
*1
0 ---
---
---
0 --- ---
*2
--- --- ---
500 ---
10 ---
0 ---
---
50
---
Note:
(1) t4=0 : concern for residual pattern before BLU turn off.
(2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value)
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
© Copyright AUO Optronics Corp. 2009 All Rights Reserved.
Page 16 / 32
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页数 | 30 页 | ||
下载 | [ T420HW06-V4.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
T420HW06-V0 | TFT LCD Module | AUO |
T420HW06-V1 | TFT LCD Module | AUO |
T420HW06-V2 | TFT LCD Module | AUO |
T420HW06-V3 | TFT LCD Module | AUO |
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