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零件编号 | T420HVD01.2 | ||
描述 | TFT LCD Module | ||
制造商 | AUO | ||
LOGO | |||
1 Page
T420HVD01.2 Product Specification
Rev.0 .0
Model Name: T420HVD01.2
Issue Date : 2012/03/16
(*)Preliminary Specifications
( )Final Specifications
Customer Signature
Date AUO
Date
Approved By
_________________________________
Approval By PM Director
Jacky Su
____________________________________
Note
Reviewed By RD Director
Eugene CC Chen
____________________________________
Reviewed By Project Leader
Sky Line
____________________________________
Prepared By PM
Jun Chang
____________________________________
© Copyright AUO Optronics Corp. 2011 All Rights Reserved.
Page 1 / 34
T420HVD01.2 Product Specification
Rev.0 .0
5. NA.
6. The measure points of VIH and VIL are in LCM side after connecting the System Board and LCM.
7. Input Channel Pair Skew Margin
Note: x = 0, 1, 2, 3, 4
8. LVDS eceiver Clock SSCG (Spread spectrum clock generator) is defined as below figures
Fclk_ss(max)
1/FSS
Fclk
Fclk_ss(min)
© Copyright AUO Optronics Corp. 2011 All Rights Reserved.
Page 8 / 34
Power Sequence for LCD
T420HVD01.2 Product Specification
Rev.0 .0
Power Supply For LCD
VDD (+12V)
GND
90%
10%
t1
Interface Signal
(LVDS Data & CLK)
GND
t2
Backlight on/off
control signal
(VBLON)
GND
Valid Data
t3
CMOS Interface Signal
(LVDS_SEL,....... )
GND
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t9
t8
Min.
0.4
0.1
450
0*1
0
---
500
10*3
0
Values
Type.
---
---
---
---
---
---
---
---
---
90%
10%
10%
t5 t6
t7
t4
t9
Max.
30
50
---
---
---
---*2
---
50
---
Unit
ms
ms
ms
ms
ms
ms
ms
ms
ms
Note:
(1) t4=0 : concern for residual pattern before BLU turn off.
(2) t6 : voltage of VDD must decay smoothly after power-off. (customer system decide this value)
(3) When CMOS Interface signal is N.C. (no connection), opened in Transmitted end, t8 timing spec can be
negligible.
© Copyright AUO Optronics Corp. 2011 All Rights Reserved.
Page 16 / 34
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页数 | 30 页 | ||
下载 | [ T420HVD01.2.PDF 数据手册 ] |
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