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PDF ( 数据手册 , 数据表 ) GX434

零件编号 GX434
描述 GX434 Monolithic 4x1 Video Multiplexer
制造商 ETC
LOGO ETC LOGO 


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GX434 数据手册, 描述, 功能
FEATURES
low differential gain: 0.03% typ. at 4.43 MHz
low differential phase: 0.012 deg. typ. at 4.43 MHz
low insertion loss: 0.05 dB max at 100 kHz
low disabled power consumption: 5.2 mW typ.
high off isolation: 110 dB at 10 MHz
all hostile crosstalk @ 5 MHz, 97 dB typ.
bandwidth (-3dB) with 30 pF load, 100 MHz typ.
fast make-before-break switching: 200 ns typ.
TTL and 5 volt CMOS compatible logic inputs
low cost 14 pin DIP and16 pin SOIC packages
optimised performance for NTSC, PAL and SECAM
applications
APPLICATIONS
Glitch free analog switching for...
• High quality video routing
• A/D input multiplexing
• Sample and hold circuits
• TV/ CATV/ monitor switching
AVAILABLE PACKAGING
14 pin DIP and 16 pin SOIC (wide)
FUNCTIONAL BLOCK DIAGRAM
IN 0 X
IN 1 X
IN 2 X
IN 3 X
OUTPUT
A0
A1
2 TO 4 DECODER
LOGIC
CHIP
SELECT
CS
GX434 Monolithic 4x1
Video Multiplexer
DATA SHEET
CIRCUIT DESCRIPTION
The GX434 is a high performance low cost monolithic 4x1
video multiplexer incorporating four bipolar switches with a
common output, a 2 to 4 address decoder and fast chip select
circuitry. The chip select input allows for multi-chip paralleled
operation in routing matrix applications. The chip is selected
by applying a logic 0 on the chip select input.
Unlike devices using MOS bilateral switching elements, these
bipolar circuits represent fully buffered, unilateral transmission
paths when selected. This results in extremely high output to
input isolation. They also feature fast make-before-break
switching action. These features eliminate such problems as
switching 'glitches' and output-to-input signal feedthrough.
The GX434 operates from ± 7 to ± 13.2 volt DC supplies. They
are specifically designed for video signal switching which
requires extremely low differential phase and gain. Logic
inputs are TTL and 5 volt CMOS compatible providing address
and chip select functions. When the chip is not selected, the
output goes to a high impedance state.
PIN CONNECTIONS
TOP VIEW
IN 0 PIN 1
GND
IN 1
GND
IN 2
GND
IN 3 7
14 +8V
AO
A1
CS
O/P
NRC
EXT
8 -8V
TOP VIEW
IN 0 PIN 1
16
GND
IN 1
GND
IN 2
GND
IN 3
NC
8
9
PIN CONNECTION
14 PIN DIP
GX434
PIN CONNECTION
16 PIN SOIC
(wide)
+8V
NC
AO
A1
CS
O/P
NRCEXT
-8V
TRUTH TABLE
CS A1 A0
00 0
00 1
OUTPUT
IN 0
IN 1
01
01
0
1
IN 2
IN 3
1X X
HI - Z
X = DON'T CARE
Document No. 510 - 34 - 2
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Japan Branch: A-302 M i yamae Vi l l age, 2–10–42 M i yamae, Suginami–ku, Tokyo 168, Japan tel. (03) 3334-7700 fax (03) 3247-8839







GX434 pdf, 数据表
2. Load Resistance Considerations
The GX434 crosspoint switch is optimised for load resistances
equal to or greater than 3 k. Figure 8 shows the effect on the
differential gain and phase when the load resistance is varied
from 100 to 100 k.
10
ƒ= 3.58 MHz, 20 IRE
BLANKING LEVEL = 0V DC
1.0
dp
0.1
dg
0.01
0.001
100
1K 10K
RL ()
Fig. 8 dg/dp vs RL
100K
The negative slew rate is dependant upon the output current
and load capacitance as shown below.
-SR = I + 3 mA
I 8 mA
CL
The current I is determined from the following equation:
I = -VEE R 1 k
R
It is possible to increase the negative slew rate (-S.R.) and thus
the large signal bandwidth, by adding a resistance from the
output to - V . This resistor increases the output current above
EE
the 3 mA provided by the internal current generator and
increases the negative slew rate. The additional slew rate
improving resistance must not be less than 1kin order to
prevent excessive currents in the output of the device. An
adverse effect of utilising this negative slew rate improving
resistor, is the increase in differential phase from typically
0.009° to 0.014°. Under these same conditions, the differential
gain drops from typically 0.033 % to 0.021 %.
+8V
IN 0
GND
IN 1
GND
IN 2
GND
IN 3
1
2
3
4
5
6
7
14
13
A0
12
A1
11
CS
10
9 NC
8
OUTPUT
R 1k
-8V
Fig.9 Negative Slew Rate (-SR) Improvement
3. Multi-chip Considerations
Whenever multi-chip bus systems are to be used, the total
input and output capacitance must be carefully considered.
The input capacitance of an enabled crosspoint (chip selected),
is typically only 2 pF and increases slightly to 2.4 pF when the
chip is disabled. The total output capacitance when the chip
is disabled is approximately 15 pF per chip.
Usually the GX434 multiplexer switch is used in a matrix
configuration of (n x 1) crosspoints perhaps combined in an
(n x m) total routing matrix. This means for example, that four
ICs produce a 16 x 1 configuration and have a total output
capacitance of 4 x15 pF or 60 pF if all four chips are disabled.
For any one enabled crosspoint, the effective load capacitance
will be 3 x15 pF or 45 pF.
In a multi-input/multi-output matrix, it is important to consider
the total input bus capacitance. The higher the bus capacitance
and the more it varies from the ON to OFF condition, the more
difficult it is to maintain a wide frequency response and
constant drive from the input buffer. A 16 x 16 matrix using 64
ICs (16 x 4), would have a total input bus capacitance of 16 x
2.4 pF or 40 pF.
1
2
3
4
GX
414
GX
414
GX
414
GX
414
5
6
7
8
GX
414
GX
414
GX
414
GX
414
9
10
11
12
GX
414
GX
414
GX
414
GX
414
n
O UTP U T B U FF E R S
1
2
3
m
Fig.10 Multi-chip Connections
510 -34 -2
8














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