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PDF ( 数据手册 , 数据表 ) W523S20

零件编号 W523S20
描述 HIGH FIDELITY PowerSpeech
制造商 Winbond
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W523S20 数据手册, 描述, 功能
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W523SXX (PRELIMINARY)
HIGH FIDELITY PowerSpeechTM
GENERAL DESCRIPTION
The W523Sxx family are programmable speech synthesis ICs that utilize Winbonds new high fidelity
voice synthesis algorithm to generate all types of voice effects with high sound quality.
The W523Sxx’ s LOAD, JUMP, MOVE and INC commands and ten programmable registers provide
powerful user-programmable functions that make this chip suitable for an extremely wide range of
speech IC applications.
The W523Sxx family includes 14 kinds of bodies which are the same except for the voice duration
shown below:
PART
NO.
W523S08 W523S10 W523S12 W523S15 W523S20 W523S25 W523S30
Duration
8 sec.
10 sec.
12 sec.
15 sec.
20 sec.
25 sec.
30 sec.
PART
NO.
Duration
W523S40
40 sec.
W523S50
50 sec.
W523S60
60 sec.
W523S70
70 sec.
W523S80
80 sec.
W523S99 W523M02
100 sec. 120 sec.
Note: The voice duration is estimated by 6.4 KHz sampling rate.
FEATURES
Operating voltage range: 2.4 – 5.5 volts for both DAC and PWM output
New high fidelity synthesis algorithm
Either PWM mode or D/A converter mode can be selected for AUD output
Provides 4 direct trigger inputs that can easily be extended to 24 matrix trigger inputs
Two trigger input debounce times (50 mS or 400 uS) can be set
Provides up to 2 LEDs and 5 STOP outputs
Flexible functions programmable through the following:
LD (Load), JP (Jump), MV (Move) and INC (Increase) commands
Four general purpose registers: R0, R1, R2 and R3
Six special purpose registers: EN0, EN1, MODE0, MODE1, STOP and PAGE
Conditional instructions: @LAST, @TGn_HIGH or LOW, where, n = 1,2,5 or 6
Speech equations
END instruction
Supports CPU interface operation
Symbolic compiler supported
Instruction cycle 400 µS typically
Section control for
Variable frequency: 4.8/6/8/12 KHz
Publication Release Date:Oct. 2000
- 1 - Revision A5







W523S20 pdf, 数据表
W523SXX (PRELIMINARY)
dependent on the MSB of data output on TG1 (Data) pin. If MSB is "1", Busy will rise after the last
rising edge of TG2 (Clock) pin. If MSB is "0", Busy will rise after the rising edge that TG1 (Data)
returns to high.
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=0
40ns
TG1
(DATA)
TG2
(CLK)
BUSY
7 bits
MSB=1
40ns
To place the W523Sxx in CPU mode, program the code according to the following example.
W523S15
CPU; Reserved word, used as a directive to notify the compiler for post processing.
LED1
FREQ2
POI:
LD MODE0,XX1XX0XXB
LD EN0, 0x00
H5+voice1+T5
END
;bit2=0 BUSY
34: ; Direct trigger or CPU interrupt.
H5+voice2+T5
END
The defaulted operating mode in W523Sxx is normal mode (or manual trigger mode), which is
identified by the "Normal" and "CPU" option control. To enter the CPU mode, the "CPU" declaration
must be inserted in the declaration region of program (*.out). In CPU mode, the bit MODE0.2, which is
defined as STPA or BUSY selection for the STPA/BUSY pin, will be selected as "0" (BUSY output)
automatically by the compiler unless otherwise specified explicitly by the STPA directive. The CPU,
STPA, and BUSY directives can appear only in the first paragraph of the *.out files so that the
compiler will automatically interpret them as Stop definitions in the POI interrupt vector. If these
directives are placed elsewhere, an error message will be issued during the compilation process.
In the program example shown above, the external µC will transfer one byte data "34" to W523Sxx.
The number 34 (Decimal) is equal to 00100010b (Binary). The interface timing is shown below.
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