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PDF ( 数据手册 , 数据表 ) ALM-81224

零件编号 ALM-81224
描述 High Linearity 1450 - 2750 MHz Variable Gain Amplifier
制造商 AVAGO
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ALM-81224 数据手册, 描述, 功能
ALM-81224
High Linearity 1450 – 2750 MHz Variable Gain Amplifier
Data Sheet
Description
Avago Technologies’ ALM-81224 is a high linearity vari-
able-gain amplifier module for use in the 1450-2750MHz
band. Gain control is achieved using a single DC voltage
input pin. High linearity is achieved through the use of
Avago Technologies’ proprietary GaAs Enhancement-
mode pHEMT process1. It is housed in a miniature 6.0
x 6.0 x 1.0 mm 24-pin Molded Chip On Board (MCOB)
package. Gain changes monotonically with gain control
pin voltage. Input is fully matched. Output match can be
tuned for optimal performance at a particular frequency
band within the VGA operation frequency range using
common RF board layout. The compact footprint coupled
with high linearity and efficiency makes ALM-81224 an
ideal choice for Basestation transmitters and receivers and
Temperature Compensation Circuitry applications.
Component Image
(6.0 x 6.0 x 1.0) mm 24-lead MCOB
AVAGO
81224
WWYY
XXXX
Note:
Package marking provides
orientation and identification
“81224 “ = Device Code
“WWYY” = Date Code identifies
month and year of
manufacturing
“XXXX” = Last 4 digit of assembly
lot number
Pin Configuration
Vdd1 GND GND GND GND Vdd2
24 23 22 21 20 19
GND 1
18 GND
RFIN 2
Q1/Q2 3
Interstage
4
GROUND
17 ½
¾ RFOUT
16 ¿
15 GND
GND 5
14 GND
GND 6
13 GND
7 8 9 10 11 12
Vc_att GND Vc1 Vc2 GND Vddbias
Features
x High Linearity at low bias current
x High max gain: 23.8 dB typ
x High linearity performance: +16.5 dBm at -65 dBc ACLR
using dual-carrier W-CDMA input signal
x Fully-matched 50 Ohm input and simple output match
x Low Noise Figure
x Built-in attenuator with monotonic response
x Variable Gain range: 38 dB typ
x GaAs E-pHEMT Technology [1]
x Small package size: 6.0 x 6.0 x 1.0 mm
Typical Performances
2140 MHz @ 5 V, 383 mA (typ)
x 23.8 dB Gain at minimum attenuation
x +16.5 dBm output power (-65 dBc ACLR) using dual-
carrier W-CDMA input signal with PAPR = 7.5 dB.
x NF: 2dB @ max gain and 16 dB @ min gain
x P1dB: 27.4 dBm
x Attenuator range: 38 dB with Vc_att: (0 V – 3.3 V)
x Shutdown current (Vc1, Vc2 = 0 V): < 30 PA
Applications
x Basestation Transmitter, Receiver and Temperature
Compensation Circuits requiring continuously variable
gain functionality
Note:
1. Enhancement mode technology employs positive Vgs, thereby
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Machine Model = 50 V
ESD Human Body Model = 500 V
Refer to Avago Application Note A004R:
Electrostatic Discharge, Damage and Control.







ALM-81224 pdf, 数据表
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
8
25° C
-40° C
85° C
10 12 14
16 18 20 22 24
Pout (dBm)
26 28 30
Figure 26. Gain vs Pout at 1840 MHz
50
48
46
44
42
40
38
36 25° C
-40° C
34 85° C
32
-20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0
Pin (dBm)
Figure 27. OIP3 vs Pin at 1840 MHz
-40
25° C
-45 -40° C
85° C
-50
-55
-60
-65
-70
-75
10 11 12 13 14 15 16 17 18 19 20 21
Pout (dBm)
Figure 28. ACLR (Dual Carrier Signal) vs Pout at 1840 MHz
-40
-45
-50
-55
-60
-65
-70 25° C
-75
-40° C
85° C
-80
10 11 12 13 14 15 16 17 18 19 20 21 22
Pout (dBm)
Figure 29. ACLR (Single Carrier Signal) vs Pout at 1840 MHz
-40
25° C
-45 -40° C
85° C
-50
-55
-60
-65
-70
-15 -12 -9 -6 -3 0 3 6 9 12 15 18 21 24 27
Gain (dB)
Figure 30. ACLR (Dual Carrier Signal) vs Gain at 1840 MHz
0.43
0.42
0.41
0.40
0.39
0.38 25° C
0.37 -40° C
0.36 85° C
0.35
0.34
0.33
10 12 14 16 18 20 22 24
Pout (dBm)
Figure 31. Idd_total vs Pout (Dual Carrier Signal) at 1840 MHz
8







ALM-81224 equivalent, schematic
Application Circuit Description and Layout
Vdd1 = +5 V
Vdd2 = +5 V
C2
L1 2.4 pF
1.9 nH
~78 mA
C18
1.0 pF
RFin C3
7.5pF
C4
7.5pF
C1 C15 C16
0.1 PF L2 7.5 pF 0.1 PF
5.6 nH
~270 mA
C17
2.2 PF
L3
1.0 nH
C19
0.3 pF
L4
1.9 nH
C14 RFout
7.5 pF
C13
2.7 pF
C12 0.1 PF
C5 C7
7.5 pF 7.5 pF
C9 C11
7.5 pF 7.5 pF
0 mA 0.1 mA
0.1 mA 40 mA
Vc_att Vc1 Vc2 Vddbias = +5 V
2.4 V 4.0 V
Figure 71. Application circuit tuned for 2140 MHz operation using 0402 size external SMT components
C1
C2
L1
C3 RFIN
C17
C16
C15
L2
RFOUT
C14
876 54321
C4
C5
C6
ALM-81224
C7
C8
C9
C10
R1
1 2345678
L3 C13 L4
C11
C12
RO4350
DK 3.48
H 10 mil
W 0.57 mm
G 0.59 mm
JUNE '10
Figure 72. Demo board diagram of application circuit for 2140 MHz
Notes:
1. The VGA is capable of wideband operation from 1450-2750 MHz. Optimum linearity and Gain at different frequencies can be tuned by changing
the values of L3, L4, C13, C19 at the output match and L1, L2 at the supply lines. Table 3 below shows the optimum linearity tuning components.
2. Optimum linearity is achieved by varying Vc1 and Vc2. Typical current is as shown in the figure above.
3. If lower output power for the same linearity is desired, then the bias currents Idd1 and Idd2 can be reduced by reducing Vc1 and Vc2 respectively.
16










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