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PDF ( 数据手册 , 数据表 ) ISL88731A

零件编号 ISL88731A
描述 SMBus Level 2 Battery Charger
制造商 Intersil Corporation
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ISL88731A 数据手册, 描述, 功能
SMBus Level 2 Battery Charger
ISL88731A
The ISL88731A is a highly integrated Lithium-ion battery
charger controller, programmable over the SMBus system
management bus (SMBus). The ISL88731A is intended to be
used in a smart battery charger (SBC) within a smart battery
system (SBS) that throttles the charge power such that the
current from the AC-adapter is automatically limited. High
efficiency is achieved with a DC/DC synchronous-rectifier buck
converter, equipped with diode emulation for enhanced light
load efficiency and system bus boosting prevention. The
ISL88731A charges one to four Lithium-ion series cells, and
delivers up to 8A charge current. Integrated MOSFET drivers
and bootstrap diode result in fewer components and smaller
implementation area. Low offset current-sense amplifiers
provide high accuracy with 10mΩ sense resistors. The
ISL88731A provides 0.5% end-of-charge battery voltage
accuracy.
The ISL88731A provides a digital output that indicates the
presence of the AC-adapter as well as an analog output which
indicates the adapter current within 4% accuracy.
The ISL88731A is available in a small 5mmx5mm 28 Ld thin
(0.8mm) QFN package. An evaluation kit is available to reduce
design time. The ISL88731A is available in Pb-Free packages.
Pin Configuration
ISL88731A
(28 LD TQFN)
TOP VIEW
Features
• 0.5% Battery Voltage Accuracy
• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBus 2 Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
- Adapter Current (3% Accuracy)
- AC-Adapter Detection
• 11-Bit Battery Voltage Setting
• 6 Bit Charge Current/Adapter Current Setting
• 8A Maximum Battery Charger Current
• 11A Maximum Adapter Current
• +8V to +28V Adapter Voltage Range
• Pb-Free (RoHS compliant)
Applications
• Notebook Computers
• Tablet PCs
• Portable Equipment with Rechargeable Batteries
Ordering Information
28 27 26 25 24 23 22
NC 1
21 VDDP
ACIN 2
20 LGATE
VREF 3
19 PGND
ICOMP 4
NC 5
18 CSOP
17 CSON
VCOMP 6
NC 7
16 NC
15 VFB
8 9 10 11 12 13 14
PART
NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL88731AHRZ ISL887 31AHRZ -10 to +100 28 Ld 5x5 TQFN L28.5x5B
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
2. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL88731A. For more information on MSL please see
techbrief TB363.
June 8, 2011
FN6738.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.







ISL88731A pdf, 数据表
ISL88731A
Functional Pin Descriptions
BOOT
High-Side Power MOSFET Driver Power-Supply Connection.
Connect a 0.1µF capacitor from BOOT to PHASE.
UGATE
High-Side Power MOSFET Driver Output. Connect to the high-side
N-Channel MOSFET gate.
LGATE
Low-Side Power MOSFET Driver Output. Connect to low-side
N-Channel MOSFET. LGATE drives between VDDP and PGND.
PHASE
High-Side Power MOSFET Driver Source Connection. Connect to
the source of the high-side N-Channel MOSFET.
CSOP
Charge Current-Sense Positive Input.
CSON
Charge Current-Sense Negative Input.
CSSP
Input Current-Sense Positive Input.
CSSN
Input Current-Sense Negative Input.
DCIN
Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to
GND.
ACIN
AC-adapter Detection Input. Connect to a resistor divider from the
AC-adapter output.
ACOK
AC Detect Output. This open drain output is high impedance
when ACIN is greater than 3.2V. The ACOK output remains low
when the ISL88731A is powered down. Connect a 10k pull-up
resistor from ACOK to VDDSMB.
ICM
Input Current Monitor Output. ICM voltage equals 20 x (VCSSP -
VCSSN).
VREF
VREF is a reference output pin. It is internally compensated. Do
not connect a decoupling capacitor.
PGND
Power Ground. Connect PGND to the source of the low side
MOSFET.
VCC
Power input for internal analog circuits. Connect a 4.7Ω resistor
from VCC to VDDP and a 1µF ceramic capacitor from VCC to
ground.
VDDP
Linear Regulator Output. VDDP is the output of the 5.2V linear
regulator supplied from DCIN. VDDP also directly supplies the
LGATE driver and the BOOT strap diode. Bypass with a 1µF
ceramic capacitor from VDDP to PGND.
ICOMP
Compensation Point for the charging current and adapter current
regulation Loop. Connect 0.01µF to GND. See “Voltage Control
Loop” on page 20 for details of selecting the ICOMP capacitor.
VCOMP
Compensation Point for the voltage regulation loop. Connect
4.7kΩ in series with 0.01µF to GND. See “Voltage Control Loop”
on page 20 for details on selecting VCOMP components.
VFB
Feedback for the Battery Voltage.
VDDSMB
SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to GND.
SDA
SMBus Data I/O. Open-drain Output. Connect an external pull-up
resistor according to SMBus specifications.
SCL
SMBus Clock Input. Connect an external pull-up resistor
according to SMBus specifications.
GND
Analog Ground. Connect directly to the backside paddle. Connect
to PGND close to the output capacitor.
Back Side Paddle
Connect the backside paddle to GND.
NC
No Connect. Pins 1, 5, 7 and 14 are not connected.
8 FN6738.3
June 8, 2011







ISL88731A equivalent, schematic
ISL88731A
Charger Timeout
The ISL88731A includes 2 timers to insure the SMBus master is
active and to prevent overcharging the battery. ISL88731A will
terminate charging if the charger has not received a write to the
ChargeVoltage or ChargeCurrent register within 175s or if the
SCL line is low for more than 25ms. If a time-out occurs, either
ChargeVoltage or ChargeCurrent registers must be written to
re-enable charging.
ISL88731A Data Byte Order
Each register in ISL88731A contains 16bits or 2, 8 bit bytes. All
data sent on the SMBus is in 8-bit bytes and 2 bytes must be
written or read from each register in ISL88731A. The order in
which these bytes are transmitted appears reversed from the
way they are normally written. The LOW byte is sent first and the
HI byte is sent second. For example, When writing 0x41A0, 0xA0
is written first and 0x41 is sent second.
Writing to the Internal Registers
In order to set the charge current, charge voltage or input current,
valid 16-bit numbers must be written to ISL88731A’s internal
registers via the SMBus.
To write to a register in the ISL88731A, the master sends a
control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL88731A it sends a register
address byte setting the register to be written (i.e. 0x14 for the
ChargeCurrent register). The ISL88731A will respond with an
Acknowledge. The master then sends the lower data byte to be
written into the desired register. The ISL88731A will respond with
an Acknowledge. The master then sends the higher data byte to
be written into the desired register. The ISL88731A will respond
with an Acknowledge. The master then issues a Stop condition,
indicating to the ISL88731A that the current transaction is
complete. Once this transaction completes, the ISL88731A will
begin operating at the new current or voltage.
ISL88731A does not support writing more than one register per
transaction.
Reading from the Internal
Registers
The ISL88731A has the ability to read from 5 internal registers.
Prior to reading from an internal register, the master must first
select the desired register by writing to it and sending the registers
address byte. This process begins by the master sending a control
byte with the R/W bit set to 0, indicating a write. Once it receives
an Acknowledge from the ISL88731A it sends a register address
byte representing the internal register it wants to read. The
ISL88731A will respond with an Acknowledge. The master must
then respond with a Stop condition. After the Stop condition, the
master follows with a new Start condition, then sends a new
control byte with the ISL88731A slave address and the R/W bit set
to 1, indicating a read. The ISL88731A will Acknowledge then
send the lower byte stored in that register. After receiving the byte,
the master Acknowledges by holding SDA low during the 9th clock
pulse. ISL88731A then sends the higher byte stored in the register.
After the second byte, neither device holds SDA low (No
Acknowledge). The master will then produce a Stop condition to
end the read transaction.
ISL88731A does not support reading more than 1 register per
transaction.
Application Information
The following battery charger design refers to the ”Typical
Application Circuit” (see Figure 2) on page 2, where typical
battery configuration of 3S2P is used. This section describes how
to select the external components including the inductor, input
and output capacitors, switching MOSFETs and current sensing
resistors.
Inductor Selection
The inductor selection has trade-offs between cost, size,
crossover frequency and efficiency. For example, the lower the
inductance, the smaller the size, but ripple current is higher. This
also results in higher AC losses in the magnetic core and the
windings, which decreases the system efficiency. On the other
hand, the higher inductance results in lower ripple current and
smaller output filter capacitors, but it has higher DCR (DC
resistance of the inductor) loss, lower saturation current and has
slower transient response. So, the practical inductor design is
based on the inductor ripple current being ±15% to ±20% of the
maximum operating DC current at maximum input voltage.
Maximum ripple is at 50% duty cycle or VBAT = VIN,MAX/2. The
required inductance for ±15% ripple current can be calculated
from Equation 3:
L = -4--------F---S---W--V---I--N--0--,--.M-3----A---X-I--L---,--M-----A----X-
(EQ. 3)
Where, VIN,(MAX) is the maximum input voltage, FSW is the
switching frequency and IL,(MAX) is the max DC current in the
inductor.
For VIN,(MAX) = 20V, VBAT = 12.6V, IBAT,(MAX) = 4.5A, and
fs = 400kHz, the calculated inductance is 9.3µH. Choosing the
closest standard value gives L = 10µH. Ferrite cores are often the
best choice since they are optimized at 400kHz to 600kHz
operation with low core loss. The core must be large enough not
to saturate at the peak inductor current IPeak in Equation 4:
IPEAK = IL, MAX + 12-- IRIPPLE
(EQ. 4)
Inductor saturation can lead to cascade failures due to very high
currents. Conservative design limits the peak and RMS current in
the inductor to less than 90% of the rated saturation current.
Crossover frequency is heavily dependent on the inductor value.
FCO should be less than 20% of the switching frequency and a
conservative design has FCO less than 10% of the switching
frequency. The highest FCO is in voltage control mode with the
battery removed and may be calculated (approximately) from
Equation 5:
FCO = -5--------1---1-2----⋅π---R----S-L---E---N----S---E-
(EQ. 5)
16 FN6738.3
June 8, 2011










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