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PDF ( 数据手册 , 数据表 ) JN5148-J01

零件编号 JN5148-J01
描述 IEEE802.15.4 Wireless Microcontroller
制造商 NXP Semiconductors
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JN5148-J01 数据手册, 描述, 功能
Data Sheet: JN5148-J01
IEEE802.15.4 Wireless Microcontroller
Overview
The JN5148-J01 is an ultra low power, high performance wireless
microcontroller targeted at JenNet and JenNet-IP networking applications.
The device features an enhanced 32-bit RISC processor offering high
coding efficiency through variable width instructions, a multi-stage
instruction pipeline and low power operation with programmable clock
speeds. It also includes a 2.4GHz IEEE802.15.4 compliant transceiver,
128kB of ROM, 128kB of RAM, and a rich mix of analogue and digital
peripherals. The large memory footprint allows the device to run both a
network stack (e.g. JenNet-IP) and an embedded application or in a co-
processor mode. The operating current is below 18mA, allowing operation
direct from a coin cell.
Enhanced peripherals include low power pulse counters running in sleep
mode designed for pulse counting in AMR applications and a unique Time
of Flight ranging engine, allowing accurate location services to be
implemented on wireless sensor networks. It also includes a 4-wire I2S
audio interface, to interface directly to mainstream audio CODECs, as well
as conventional MCU peripherals.
Block Diagram
2.4GHz
Radio
XTAL
Watchdog
Timer
Power
Management
Time of Flight
Engine
O-QPSK
Modem
RAM ROM
128kB 128kB
32-bit
RISC CPU
IEEE802.15.4
MAC
Accelerator
32-byte
OTP eFuse
128-bit AES
Encryption
Accelerator
SPI
2-Wire Serial
Timers
UAR Ts
4-Wire Audio
Sleep Counters
12-bit ADC,
Comparators
12-bit DACs,
Temp Sensor
Benefits
Single chip integrates
transceiver and
microcontroller for wireless
sensor networks
Large memory footprint to
run JenNet-IP or JenNet
together with an application
Very low current solution for
long battery life
Highly featured 32-bit RISC
CPU for high performance
and low power
System BOM is low in
component count and cost
Extensive user peripherals
Applications
Robust and secure low power
wireless applications
JenNet-IP and JenNet networks
Smart metering
(e.g. AMR)
Home and commercial building
automation
Location Aware services – e.g.
Asset Tracking
Industrial systems
Telemetry
Remote Control
Toys and gaming peripherals
Features: Transceiver
2.4GHz IEEE802.15.4 compliant
Time of Flight ranging engine
128-bit AES security processor
MAC accelerator with packet
formatting, CRCs, address check,
auto-acks, timers
500 & 667kbps data rate modes
Integrated sleep oscillator for low
power
On chip power regulation for 2.0V
to 3.6V battery operation
Deep sleep current 100nA
Sleep current with active sleep
timer 1.25µA
<$0.50 external component cost
Rx current 17.5mA
Tx current 15.0mA
Receiver sensitivity -95dBm
Transmit power 2.5dBm
Features: Microcontroller
Low power 32-bit RISC CPU, 4 to
32MHz clock speed
Variable instruction width for high
coding efficiency
Multi-stage instruction pipeline
128kB ROM and 128kB RAM for
bootloaded program code & data
JTAG debug interface
4-input 12-bit ADC, 2 12-bit
DACs, 2 comparators
3 application timer/counters,
2 UARTs
SPI port with 5 selects
2-wire serial interface
4-wire digital audio interface
Watchdog timer
Low power pulse counters
Up to 21 DIO
Industrial temp (-40°C to +85°C)
8x8mm 56-lead Punched QFN
Lead-free and RoHS compliant
© NXP Laboratories UK 2013
JN-DS-JN5148-J01 1v2
1







JN5148-J01 pdf, 数据表
1.4 Block Diagram
Tick Timer
Programmable
Interrupt
Controller
Fro m Perip herals
32-bit RISC CPU
VB_XX
VDD1
VDD2
RAM
128kB
RESET N
XT AL_IN
XT AL_OUT
ROM
128kB
OTP
eFuse
Voltage
Regulators
Reset
Wakeup
Timer0
Wakeup
Timer1
1.8V
Brown-out
Detect
Watchdog
Timer
32kHz Clock
Select
32kHz
RC
Os c
32kHz
Cl oc k
Gen
32MHz Clock
Generator
32KIN
CPU and 16MHz
System Clock
32KXTALIN
32KXTALOUT
Clock Divider
Multiplier
24MHz
RC Osc
ADC1
ADC2
ADC3
ADC4
DAC1
DAC2
COMP1M/
EXT _PA_B
COMP1P/
EXT _PA_C
COMP2M
COMP2P
Supply Monitor
M
U ADC
X
Temperature
Sensor
DAC1
DAC2
Comparator1
Comparator2
Sample
FIFO
SPI
Master
SPISEL1
SPISEL2
SPISEL3
SPISEL4
UART0
UART1
Timer0
Timer1
Timer2
2-wire
Interf ace
Intelligent
Peripheral
Pulse
Counters
JTAG
Debug
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM0OUT
TIM0CAP
TIM1CK_GT
TIM1OUT
TIM1CAP
TIM2OUT
SIF_D
SIF_CLK
IP_DO
IP_DI
IP_INT
IP_CLK
IP_SEL
PC0
PC1
J TA G_TDI
J TA G_TMS
J TA G_TCK
J TA G_TDO
MUX
Antenna
Div ersity
ADO
ADE
4-wire
Digital
Audio
Interf ace
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
Wireless
Transceiv er
Security
Coprocessor
SPICLK
SPIMOSI
SPIMISO
SPISEL0
DIO0/SPISEL1
DIO1/SPISEL2/PC0
DIO2/SPISEL3/RFRX
DIO3/SPISEL4/RFTX
DIO4/CTS0/JT AG_T CK
DIO5/RTS0/JT AG_T MS
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_T DI
DIO8/T IM0CK_GT /PC1
DIO9/T IM0CAP/32KXTALIN/32KIN
DIO10/T IM0OUT /32KXT ALOUT
DIO11/T IM1CK_GT /T IM2OUT
DIO12/T IM1CAP/ADO/DAI_WS
DIO13/T IM1OUT /ADE/DAI_SDIN
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DDIIOO1166/R/IPX_DD1I/IP_DI/JT AG_TDI
DIO17/CT S1/IP_SEL/DAI_SCK/
JTAG_T CK
DIO18/RT S1/IP_INT /DAI_SDOUT /
JTAG_T MS
DIO19/T XD1/JTAG_T DO
DIO20/RXD1/JT AG_T DI
T ime
Of
Flight
Digital
Baseband
Radio
RF_IN
VCOT UNE
IBAIS
Figure 1: JN5148 Block Diagram
8
JN-DS-JN5148-J01 1v2
© NXP Laboratories UK 2013







JN5148-J01 equivalent, schematic
4 Memory Organisation
This section describes the different memories found within the JN5148. The device contains ROM, RAM, OTP eFuse
memory, the wireless transceiver and peripherals all within the same linear address space.
0xFFFFFFFF
0xF0020000
RAM
(128kB)
0xF0000000
Unpopulated
0x04000000
0x02000000
0x00020000
RAM Echo
Peripherals
ROM
(128kB)
0x00000000
Figure 5: JN5148 Memory Map
4.1 ROM
The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle. The ROM
contents include bootloader to allow external Flash memory contents to be bootloaded into RAM at runtime, a default
interrupt vector table, an interrupt manager, IEEE802.15.4 MAC and APIs for interfacing on-chip peripherals. The
operation of the boot loader is described in detail in Application Note [7]. The interrupt manager routes interrupt calls
to the application’s soft interrupt vector table contained within RAM. Section 7 contains further information regarding
the handling of interrupts. ROM contents are shown in Figure 6.
0x00020000
Spare
JenNet Stack
APIs
IEEE802.15.4
Stack (inc MAC)
Boot Loader
Interrupt Manager
Interrupt Vectors
0x00000000
Figure 6: Typical ROM contents
16
JN-DS-JN5148-J01 1v2
© NXP Laboratories UK 2013










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