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PDF ( 数据手册 , 数据表 ) HCF4029B

零件编号 HCF4029B
描述 BINARY OR BCD DECADE PRESETTABLE UP/DOWN COUNTER
制造商 STMicroelectronics
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HCF4029B 数据手册, 描述, 功能
HCC4029B
HCF4029B
PRESETTABLE UP/DOWN COUNTER
BINARY OR BCD DECADE
. MEDIUM SPEED OPERATION - 8MHz (typ.) @
CL = 50pF AND VDD-VSS = 10V
. MULTI-PACKAGE PARALLEL CLOCKING FOR
SYNCHRONOUS HIGH SPEED OUTPUT RES-
PONSE OR RIPPLE CLOCKING FOR SLOW
CLOCK INPUT RISE AND FALL TIMES
. ”PRESET ENABLE” AND INDIVIDUAL ”JAM”
INPUTS PROVIDED
. BINARY OR DECADE UP/DOWN COUNTING
. BCD OUTPUTS IN DECADE MODE
. STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
. 5V, 10V, AND 15V PARAMETRIC RATINGS
. INPUT CURRENT OF 100nA AT 18V AND 25°C
FOR HCC DEVICE
. QUIESCENT CURRENT SPECIFIED TO 20V
FOR HCC DEVICE
. 100% TESTED FOR QUIESCENT CURRENT
. MEETS ALL REQUIREMENTS OF JEDECTEN-
TATIVE STANDARD No. 13A, ”STANDARD
SPECIFICATIONS FOR DESCRIPTION OF ”B”
SERIES CMOS DEVICES”
EY
(Plastic Package)
F
(Ceramic Package)
M1
(Micro Package)
C1
(Chip Carrier)
ORDER CODES :
HCC4029BF
H CF 4029 BM 1
HCF4029BEY
H CF 4029 BC 1
DESCRIPTION
The HCC4029B (extended temperature range) and
HCF4029B (intermediate temperature range) are
monolithic integrated circuit, available in 16-lead
dual in-line plastic or ceramic package and plastic
micro package. The HCC/HCF4029B consists of a
four-stage binary or BCD-decade up/down counter
with provisions for look-ahead carry in both counting
modes. The inputs consist of a single CLOCK,
CARRY-IN (CLOCK ENABLE), BINARY/DECADE,
UP/DOWN, PRESET ENABLE, and four individual
JAM signals. Q1, Q2, Q3, Q4 and a CARRY OUT
signal are provided as outputs. A high PRESET EN-
ABLE signal allows information on the JAM INPUTS
to preset the counter to any state asynchronously
with the clock. A low on each JAM line, when the
PRESET-ENABLE signal is high, resets the counter
to its zero count. The counter is advanced one count
at the positive transition of the clock when the
CARRY-IN and PRESET ENABLE signals, are low.
Advancement is inhibited when the CARRY-IN or
PRESET ENABLE signals are high. The CARRY-
OUT signal is normally high and goes low when the
PIN CONNECTIONS
NC = No Internal Connection
September 1988
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HCF4029B pdf, 数据表
HCC/HCF4029B
APPLICATIONS
Conversion of Clock up, Clock Down Input Sig-
nals to Clock and Up/Down Inputs Signals.
The HCC/HCF4029B CLOCK and UP/DOWN in-
puts are used directly in most applications. In appli-
cations where CLOCK UP and CLOCK DOWN
inputs are provided, conversion to the
HCC/HCF4029B CLOCK and UP/DOWN inputs
can easily be realized by use of the circuit.
HCC/HCF4029B changes count on positive transi-
tions of CLOCK UP or CLOCK DOWN inputs. For
the gate configuration shown below, when counting
up the CLOCK DOWN input must be maintained
high and conversely when counting down the
CLOCK UP input must be maintained high.
Cascading Counter Packages.
* CARRY-OUT lines at the 2nd, 3rd, et., stages may have a negative-going glitch pulse resulting from differential delays of different
HCC/HCF4029B IC’s. These negative-going glitches do not affect proper HCC/HCF4029B operation. However, if the CARRY-OUT signals
are used to trigger other edge-sensitive logic devices, such as FF’s or counters, the CARRY-OUT signals should be gated with the clock signal
using a 2-input NOR gate such as HCC/HCF4001B.
Ripple Clocking Mode : The Up/Down control can be changed at any count. The only restriction on changing the Up/Down control is that the
clock input to the first counting stage must be high.
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