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PDF ( 数据手册 , 数据表 ) MZ-700

零件编号 MZ-700
描述 PERSONAL COMPUTER SERVICE MANUAL
制造商 Sharp
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MZ-700 数据手册, 描述, 功能
MZ-700
- r '. . . . .S. . .H. . .A. . .R. . . .P. . . . .S. .E. .R. . .V. .I.C. .E. . . .M. . A. . .N. .U. .A. . .L. . . . . . . . . .. .
CODE: OOZMZ700SM I/E
PERSONAL COMPUTER
MODEL MZ-700
MZ-1TOl
MZ-1POl
(FOR THE MZ-lPOI MECHANICAL SECTION
REFER TO THE DPG2306 SERVICE MANUAL)
INDEX
1. SPECIFICATIONS. . . . . . . . . . . . . . . . . .. . . . . . .. . . . . . .. . . .. . . .. 1
2. NAMES OF FUNCTIONAL COMPONENTS. . . . . . . . . . . . . . . . . . . .. 2
3. SYSTEM BLOCK DIAGRAM .............................. _.. 3
4. SYSTEM DESCRIPTION. . . . . . . . . . . . . • . . . . . . . . . . . . . •. . . . . . .. 4
5. DATA RECORDER .................................... .... 15
6. COLOUR ENCODER ....... . ........ . . .. ...... . ............ 19
7. MICRO COLOUR GRAPHIC PRINTER ......................... 20
8. POWER SUPPLy ................... . ............. ........ 24
9. IC SIGNAL POSITION .......................•........... . . 27
10. CIRCUIT DIAGRAM & PARTS LAyOUT ...•. .. ... .. .... .. .... 29
11. PARTS GUIDE & LIST
SHARP CORPORATION







MZ-700 pdf, 数据表
\ ,'1Z - 7 0 0
2) Memory controller
In the MZ·700, it needs to segregate the memory in order
to acheive the above mentioned memory mapping. The
memory controller is therefore used to perform address
management of peripherals assigned to the memory such
as DRAM, monitor ROM, video RAM, and keyboard. The
bank select method is used to switch memory. Memory
selection is acheived using the OUT command.
I/O
port
$0000
~
$OFFF
$DOOOO
l
$FFFF
INHl INH2 INH3
$EO D·RAM
$El -
-
D-RAM
L-
-
- L-
$E2
MONITOR
ROM
-
H-
-
$E3 -
V·RAM,8255
8253
-
H-
$E4
MONITOR V·RAM,8255
ROM
8253
H
H
H
$E5 -
Prohibited
-
-
L
$E6 -
Returns to the
state before - - H
prohibitied.
INHl - INH3 are custom LSI internal signals which cause
the memory map to change.
INH1
H
L
H
H
INH2
H
H
L
H
INH3
H
H
H
L
1--:-.:-:-:---1 I : : : II--D-_R:_:_M---I
I---D-_:_OA_MM----j
V·RAM
V·RAM
D-RAM
INH1
INH2
INH3
L
L
H
D·RAM
D-RAM
D·RAM
H
L
L
ROM
D-RAM
L
H
L
D-RAM
D-RAM
L
L
L
D-RAM
D·RAM
NOTE: The command with which the memory selection is
to be done should not be written in the memory
block to be selected.
• Custom LSI internal memory controller block diagram
and description
When the above mentioned OUT command is executed,
address Ao ,.., A2 is stored in "FF" to create INHl ,..,
INH3, then ROM, VRAM, and DRAM may be accessed
against CPU addressing on the basis of those INH signals.
RA~ becomes active when the DRAM is accessed.
• CSO becomes active when the monitor ROM is accessed.
• CSE becomes active when the memory mapped I/O
(8255,8253) is accessed.
• CSDN (internal signal) becomes active when the VRAM
is accessed. If in the blnk period, CSDD becomes active.
So that, the address from the CPU is sent of Po ,.., PlO.
• If the display period is on when accessing the ROM or
VRAM, WATN becomes active.
• line address and row address switching signal (LS157
input) when accessing the RAM is derived from PHI,
WRN, MRQN, and RDN. As WR rises before the falling
edge of CAS during the write cycle, it becomes an early
cycle.
7







MZ-700 equivalent, schematic
5. DATA RECORDER
5-1. Data recorder (MZ-lT01)
Data transfer with the recorder is carried out via the 8255.
The read data is sent out through the port Cl and the
write data is received through the port C5. The motor
on/off control is carried out via the port C3 and that
activation of the motor is confmned through the port C4.
The signal SENSE goes low when FF, REW, or PLAY
pushbutton is pushed on the MZ-} TO I.
• Cassette specification
Method
Rated power
Rated current
PWM recording method
5V ± O.25V
Wait:
2mA
Record: 210mA (TEAC TEST TAPE)
Playback: 150mA (TEAC TEST TAPE)
Semiconductors used
Tape used
Rated tape speed
Tracks
Motor
Bias
Erasure
Transistor x 5
IC x 2
Diode x4
C30 - C90
4.75cm/sec
2 tracks, monoral
5V electronic governor motor
DC
DC
Standard playback point lmsec - 500 sec
Nominal input
level and
input impedance
L: O.4V, max.
H: 2.0V, min.
R~cording terminallOkn min.
Nominal input level
L: O.4V, max.
H: 2.0V, min.
Block diagram
Erase head - - - - - - Record/playback head TAPE
Control
circuit
Differentiation
+o5
V-_
_~_
_
_
_
_
_
_
_
_
_
_
_
_
_~_
_~_
_
_
_
_
_
_
_
_
_
_
_~_
_
_
_ circuit
~03003
SW3002
R3003
R3004
Amplifier
03003
Mechanically interlinked switch
WRITE
Amplifier
circuit
03001
03002
Amplifier/
+5-V~---!
Limiter
circuit(1/2),
IC3001
Waveform
shaping
circuit (2/2),
IC3001
READ
15
Amplifier
circuit,
03004










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