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PDF ( 数据手册 , 数据表 ) K4B1G1646E

零件编号 K4B1G1646E
描述 1Gb E-die DDR3 SDRAM
制造商 Samsung
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K4B1G1646E 数据手册, 描述, 功能
Rev. 1.4, Nov. 2009
K4B1G0446E
K4B1G0846E
K4B1G1646E
1Gb E-die DDR3 SDRAM
60FBGA & 84FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2009 Samsung Electronics Co., Ltd. All rights reserved.
-1-







K4B1G1646E pdf, 数据表
K4B1G0446E
K4B1G0846E
K4B1G1646E
datasheet
Rev. 1.4
DDR3 SDRAM
3.3 x16 Package Pinout (Top view) : 96ball FBGA Package
1
2
3 456 7
8
A
VDDQ
DQU5
DQU7
B VSSQ VDD
VSS
C
VDDQ
DQU3
DQU1
D
VSSQ
VDDQ
DMU
E
VSS
VSSQ
DQL0
F
VDDQ
DQL2
DQSL
G
VSSQ
DQL6
DQSL
H
VREFDQ
VDDQ
DQL4
J NC VSS RAS
K ODT VDD CAS
L NC CS WE
M VSS BA0 BA2
N VDD
A3
A0
P VSS
A5
A2
R VDD
A7
A9
T VSS RESET NC
DQU4
DQSU
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK
A10/AP
NC
A12/BC
A1
A11
NC
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQL5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through the package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
-8-







K4B1G1646E equivalent, schematic
K4B1G0446E
K4B1G0846E
K4B1G1646E
datasheet
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
VIH.DIFF.AC.MIN
tDVAC
VIH.DIFF.MIN
Rev. 1.4
DDR3 SDRAM
0.0
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
half cycle
tDVAC
time
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Differential AC & DC Input Levels
Symbol
Parameter
DDR3-800/1066/1333/1600
min max
unit NOTE
VIHdiff
VILdiff
VIHdiff(AC)
VILdiff(AC)
differential input high
differential input low
differential input high ac
differential input low ac
+0.2
NOTE 3
2 x (VIH(AC)-VREF)
NOTE 3
NOTE 3
-0.2
NOTE 3
2 x (VREF - VIL(AC))
V
V
V
V
1
1
2
2
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low
level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max,
VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification "
[ Table 10 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
Slew Rate [V/ns]
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
min max
> 4.0
75 -
4.0 57 -
3.0 50 -
2.0 38 -
1.8 34 -
1.6 29 -
1.4 22 -
1.2 13 -
1.0 0 -
< 1.0
0-
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min max
175 -
170 -
167 -
163 -
162 -
161 -
159 -
155 -
150 -
150 -
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