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PDF ( 数据手册 , 数据表 ) A025DL02-V3

零件编号 A025DL02-V3
描述 LCD Module
制造商 AUO
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A025DL02-V3 数据手册, 描述, 功能
www.DataSheet4U.net
Gleichmann & Co. Electronics GmbH
Product Marketing Displays & Systems
Industriestr. 16, D- 76297 Stutensee
Tel :07249-910-0, Fax: 07249-910-559
http://www.msc-ge.com
Doc. version: 1
Tota l pa g es: 40
Date
: 2005/10/24
Product Specifications
2.5COLOR LTPS TFT-LCD MODULE
MODEL NAME: A025DL02 V3
<>Preliminary Specifications
< > Final Specifications
Note: The content of the
specifications is subject to
change.
© 2005 AU Optronics
All Rights Reserved,







A025DL02-V3 pdf, 数据表
www.DataSheet4U.net
Version: 1
Page: 7 / 40
Note 4: VGH and VGL are output voltages of integrated LCD driver IC.
Note 5: The brightness of LCD panel could be adjusted by the adjustment of the AC component of VCOM.
Note 6: VCDC could be adjusted, so as to minimize flicker and maximum contrast on each module.
c. Recommended Capacitance Values of External Capacitor
The recommended capacitance values of the external capacitor are shown below. These values
should be finally determined only after performing sufficient evaluation on the module.
Pin name
AVDD
VGH
VGL
VCOMH
VCOML
V1, V2
V3, V4
V5, V6
V7, V8
V9, V10
Recommended value of
capacitors (µF)
4.7 to 10
4.7 to 10
4.7 to 10
4.7 to 10
4.7 to 10
2.2 to 10
2.2 to 10
2.2 to 10
2.2 to 10
2.2 to 10
Withstanding
voltage (V)
16
16
16
16
16
16
16
16
16
16
d. Backlight driving conditions
Parameter
Symbol
Min.
Typ.
Max.
LED current
20
LED voltage
VL
7.8
LED Life Time
LL 10000
Note 1 : Ta. = 25, IL = 20mA
Note 2 : Brightness to be decreased to 50% of the initial value
Unit
mA
V
Hr
Remark
Note 1,2
4. AC Timing
a.UPS051 Timing conditions (refer to Fig. 1, Fig. 2)
Parameter
DCLK Frequency
Period
Display period
HSYNC Blanking
Front porch
Pulse width
VSYNC Period
Display period
Blanking
Symbol
1/tDCLK
tH
thdisp
thblk
thfp
thsw
tV
tvdisp
tvblk
Min.
16.89(*)
1149
66
123
1
245
3
Typ.
24.535
1560
960
241
359
1
262.5
240
21
Max.
27
1716
255
thblk -1
31
Unit.
MHz
DCLK
DCLK
DCLK
DCLK
DCLK
tH
tH
tH
Remark
Note 1
Note 2
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.







A025DL02-V3 equivalent, schematic
www.DataSheet4U.net
CCIR656 Timing chart
Version: 1
Page: 15 / 40
DCLK
(27MHz)
D[7..0]
Invalid Data
FFh 00h 00h XY Cb0 Y0
(SAV)
Cr0 Y1
Cb
718
Y718
Cr
718
Y719
FFh
00h
00h
XY
720 CCIR valid data
(EAV)
Invalid
Data
Fig. 5: CCIR656 Data input format
CCIR656 decoding
FF 00 00 XY signals are involved with HSYNC,VSYNC and Field
XY encode following bits:
F=field select
V=indicate vertical blanking
H=1 if EAV else 0 for SAV
P3-P0=protection bits
P3=VH P2=FH P1=FV P0=FVH
represents the exclusive-OR function.
Control is provided through “End of Video” (EAV) and “Start of Video” (SAV) timing references.
Horizontal blanking section consists of repeating pattern 80 10 80 10
XY
D7(MSB) D6 D5 D4 D3 D2 D1 D0(LSB)
1 F V H P3 P2 P1 P0
CCIR656 to RGB conversion
R=Y +1.371*(Cr-128)
G=Y -0.698(Cr-128)-0.336(Cb-128)
B=Y +1.732(Cb-128)
Where Y:16~235 Cr:16~240 Cb:16~240
In CCIR656 mode , please set series command R3=2Eh & R13=4Bh for the better contrast .
ALL RIGHTS STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR
TRANSFORMED TO ANY OTHER FORMS WITHOUT PERMISSION FROM AU OPTRONICS CORP.










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